Patent
1993-12-15
1997-02-18
Sheikh, Ayaz R.
395561, G06F 900
Patent
active
056049099
ABSTRACT:
A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.
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Hsu Peter
Joshi Chandra
Nofal Monica R.
Rodman Paul
Sheikh Ayaz R.
Silicon Graphics Computer Systems, Inc.
Wiley David A.
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