Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2001-08-16
2004-11-02
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C712S300000, C708S209000
Reexamination Certificate
active
06813657
ABSTRACT:
TECHNICAL FIELD
A bit stream processing apparatus for storing a bit stream in a circular buffer without separately storing a header and data of the bit stream is disclosed.
DESCRIPTION OF THE RELATED ART
Generally, an apparatus for processing a bit stream that is coded based on a frame sequentially stores the bit stream into a buffer and then processes the bit stream. Since the bit stream stored in the buffer is not aligned based on a byte or a word, and the number of bits required to process the bit stream is different for different cases, an aligner is needed for aligning the required bits.
FIG. 1
is a diagram showing a moving pictures expert group (MPEG) layer
3
audio frame format. As shown in
FIG. 1
, when the bit stream is coded based on a frame, a portion of the i-th frame data is stored in an unused portion of the (i−1)-th frame. Here, a pointer MB contained in a header H
i
of the i-th frame F
i
has a value identical to or smaller than zero and indicates a starting point of the i-th frame data stored in the (i−1)-th frame F
i−1
.
For processing such a bit stream, additional hardware is needed for dividing the buffer into a header buffer and a data buffer and for decoding a header of the inputted bit stream to classify it as a header or as data. As a result, the design of the bit stream processing unit is very complicated. Additionally, since different hardware is needed for different types of bit streams, a newly designed bit stream processing unit is required for processing each new type of bit stream.
SUMMARY OF THE DISCLOSURE
An apparatus is provided for processing a bit stream. The apparatus includes a circular buffer for storing a transmitted bit stream; a first register for storing data indicating a first read point of the bit stream stored in the circular buffer; and a first backup register for backing up the data stored in the first register. The apparatus also includes a second register for storing data indicating a number of bits to be read from the circular buffer; a third register for storing data indicative of the number of bits to be ignored from the read point; and a second backup register for backing up the data stored in the third register. In addition, the apparatus is provided with an adder for adding the data stored in the second register and the data stored in the third register; and a controller responsive to the adder to determine a number of bits to be shifted to read desired data from the circular buffer.
An apparatus is also provided for reading data from a circular buffer storing data in a plurality of memory words. The apparatus includes a first storage device for storing data indicative of a desired number of bits to be read; a second storage device for storing data indicative of a first bit to be read in a first memory word; and a shifter for receiving data stored in the first memory word and data stored in the second memory word located adjacent the first memory word in the circular buffer. The apparatus also includes a logic circuit in communication with the first and second storage devices for controlling the shifter to shift a number of bits specified by the data in the first and second storage devices to align the data in the shifter in a read position.
An apparatus is also provided for reading data from a circular buffer storing data in a plurality of memory words which includes a first masking circuit and a second masking circuit. The first masking circuit receives data contained in at least two memory words of the circular buffer. The at least two memory words include data to be read. When a rightmost bit of the received data is not part of the data to be read, the first masking circuit outputs a subset of the received data which includes at least the data to be read but excludes at least the rightmost bit. The second masking circuit masks unwanted bits from the output of the first masking circuit.
Further, a method is provided for reading data from a circular buffer storing data in a plurality of memory words. The method comprises the steps of: identifying at least one of the memory words containing data to be read; identifying a number of bits to be read; identifying a first bit to be read; retrieving all data in the memory words of the circular buffer storing data to be read; inputting the retrieved data to a shifter; summing the number of bits to be read with a number of bits to be ignored adjacent the first bit to be read to develop a sum; subtracting the sum from a predetermined number to determine a shift amount; shifting the data in the shifter by the shift amount to remove unwanted bits adjacent a last bit to be read; masking unwanted bits adjacent the first bit to be read; and outputting the bits to be read.
REFERENCES:
patent: 5526296 (1996-06-01), Nakahara et al.
patent: 5619715 (1997-04-01), Dinkjian et al.
patent: 5822620 (1998-10-01), Malik et al.
patent: 5835793 (1998-11-01), Li et al.
patent: 6065107 (2000-05-01), Luick
patent: 2001/0020266 (2001-09-01), Kojima et al.
Hyundai Electronics Industries Co,. Ltd.
Marshall & Gerstein & Borun LLP
Martinez David
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