Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-10-15
2001-08-14
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S168000, C711S210000, C710S005000
Reexamination Certificate
active
06275914
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to memory architectures for computer systems. More specifically, the present invention relates to a method and an apparatus for preserving the ordering of memory requests directed to multiple memory controllers.
2. Related Art
As computer systems grow increasingly more sophisticated, they are beginning to include multiple functional units. For example, it is common for a computer system to include one or more central processing units (CPUs) as well as a graphics processor and various DMA devices. As the number of functional units in a computer system increases, the computer system's memory comes under increasing pressure to service memory requests. Consequently, the memory can become a bottleneck to computer system performance.
One solution to this problem is to incorporate multiple memory channels in a computer system, wherein each memory channel handles accesses to a different region of memory. These multiple memory channels can work in parallel to service memory requests from the multiple functional units.
In designing a system with multiple memory channels, it is important to allow each functional unit to access to all of the memory channels, so that each functional unit can access all of the regions of memory. One problem in doing so is that memory requests from a given functional unit may return out of order from different memory controllers. This can create problems if there are dependencies between the memory requests. One solution to this problem is to provide additional circuitry at the functional unit to ensure that memory requests are executed in order. However, this complicates the design of the functional unit and may limit the performance advantages of queuing requests at memory controllers.
Another solution is to include circuitry within the memory controllers to ensure that requests from a given functional unit are issued in order. This simplifies the design of functional units and can improve overall computer system performance. However, this requires the memory controllers to communicate information with each other, which can cause prohibitively large communication delays.
What is needed is a method and an apparatus that enables multiple memory controllers to ensure that requests from functional units are issued in order without incurring large communication delays.
SUMMARY
One embodiment of the present invention provides an apparatus that preserves ordering of memory requests distributed across multiple memory controllers. The apparatus includes a first memory controller containing a receiving circuit that is configured to receive a memory request that includes a source tag indicating a source from which the memory request originated. For example, a source tag may identify a processor or a graphics accelerator. The apparatus also includes a comparison circuit that compares the source tag with source tags for pending memory requests in a second memory controller to determine if the second memory controller contains any pending memory requests from the same source. Note that the source tags for the second memory controller are contained within a storage area in the first memory controller. The apparatus also includes a request order enforcement circuit that is configured to prevent the memory request from issuing from the first memory controller before the pending memory requests from the same source within the second memory controller complete. The apparatus additionally includes an issuing circuit that is configured to issue the memory request from the first memory controller to a first random access memory coupled to the first memory controller.
In one embodiment of the present invention, the apparatus additionally includes a propagation circuit that is configured to propagate the source tag for the memory request to the second memory controller so that the second memory controller can compare source tags for subsequent requests received at the second memory controller against source tags for pending memory requests in the first memory controller.
In one embodiment of the present invention, the storage area within the first memory controller for storing the source tags from the second memory controller is organized as a FIFO circuit.
In one embodiment of the present invention, the comparison circuit is further configured to compare the source tag with source tags for pending memory requests in a third memory controller to determine if the third memory controller contains any pending memory requests from the same source. Additionally, the it request order enforcement circuit is further configured to prevent the memory request from completing until the pending memory requests from the same source within the third memory controller complete.
In one embodiment of the present invention, the request order enforcement circuit is configured to stall the first memory controller until the pending memory requests within the second memory controller from the same source complete.
In one embodiment of the present invention, the request order enforcement circuit is configured to stall pending memory requests in the first memory controller.
In one embodiment of the present invention, the receiving circuit is further configured to receive a time stamp associated with the memory request, and the comparison circuit is further configured to compare the time stamp associated with the memory request against time stamps associated with the pending memory requests in the second memory controller.
In one embodiment of the present invention, the issuing circuit is further configured to receive a response from the first random access memory indicating that the memory request has been completed, and to return read data to the source from which the memory request originated if the memory request is a read operation.
REFERENCES:
patent: 4733352 (1988-03-01), Nakamura et al.
patent: 5442755 (1995-08-01), Shibata
patent: 5603005 (1997-02-01), Bauman et al.
patent: 6167492 (2000-12-01), Keller et al.
Kim Matthew
Micron Technology Inc
Park Vaughan & Fleming LLP
Tran Denise
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