Apparatus for performing a low latency memory read with concurre

Details Apparatus for performing a low latency memory read with concurre Apparatus for performing a low latency memory read with concurre

1997-07-02

2000-01-25

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711144, 711154, G06F 1200, G06F 1300

Patent

active

060187921

ABSTRACT:
A computer system has a system memory, cache memory, system controller that process memory transactions. The system controller transmits a memory request to the system memory without waiting for the cache memory to be snooped to determine whether the cache memory stores information in an address corresponding to a selected address of the system memory. The system controller may transmit a snoop request to the cache memory concurrently with or after the memory request is transmitted to the system memory. The system controller may have a control switch that uses a first pathway for the memory request and a second pathway for the snoop request so that the snoop and memory requests can be transmitted simultaneously.

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Shanley and Anderson, "ISA System Architecture," Addison-Wesley Publishing Co., 3.sup.rd Ed., pp. 235-272, Feb. 1995.

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