Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-13
2003-06-24
Tran, M. (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06584598
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to characterizing electronic circuits and, more particularly, to characterizing constraints of electronic circuits.
BACKGROUND
Complexity of a typical electronic circuit, for example, an integrated-circuit device, has increased dramatically. At the same time, the length of the design cycle has typically remained unchanged or has become shorter. To meet the shorter design cycles for the more complex designs, circuit designers increasingly rely on characterization of the designs in order to identify any problems early in the design cycle. The short design cycles and the complexity of the integrated-circuit devices make cost- and time-prohibitive an approach that characterizes a design by actually realizing the design in hardware and testing it in a laboratory.
As an alternative to actually building a prototype of the design, circuit designers have increasingly relied on electronic design automation (EDA) tools, such as circuit simulation and characterization tools. Effective circuit simulation tools provide a way for the designer to simulate the behavior of a complex design, identify any problems, and make alterations and enhancements to the circuit before arriving at a final design. That iterative design process has in turn improved the reliability of the end-products that incorporate a given circuit design. The effectiveness of a circuit characterization or simulation tool depends on several criteria, for example, accuracy, reliability, and predictability. Traditional approaches to characterizing circuit constraints or various attributes of circuits, for example, intrinsic delay, output transition time, or power, sometimes fail to meet those criteria. In other words, the traditional approaches may fail to provide results that match the behavior of an actual prototype relatively closely. The failure of the traditional characterization techniques results in increased costs, longer design cycles, less reliable end-products, and/or less-than-optimal designs. A need therefore exists for accurate and reliable techniques for circuit characterization and circuit-constraint characterization.
SUMMARY OF THE INVENTION
The invention contemplates constraint characterization in electronic cells or circuits. One aspect of the invention relates to circuit-characterization systems. In one embodiment of the invention, a circuit-characterization system includes a computer configured to characterize a first constraint of a circuit according to a model of an operation of the circuit to select a value for the first constraint. The computer characterize a second constraint of the circuit according to the model of the operation of the circuit to select a value for the second constraint. The computer modifies the values selected for the first and second constraints to obtain optimized values for the first and second constraints, respectively. The optimized values of the first and second constraints avoid an invalid region of operation of the circuit.
In another embodiment, a circuit-characterization system includes a computer configured to characterize a first constraint of an electronic circuit according to a model of an operation of the circuit to acquire a value for the first constraint. The computer also characterizes a second constraint of the circuit according to the model of the operation of the electronic circuit to acquire a value for the second constraint. The second constraint is characterized independently of the characterization of the first constraint. The computer obtains optimized values of the first and second constraints, by modifying the values acquired for the first and second constraints, respectively, so as to avoid an invalid meta-stable region of operation of the circuit.
More specifically, the computer is configured to characterize the first constraint by using a first degraded characteristic of the electronic circuit obtained according to a first degradation option. The computer is also configured to characterize the second constraint by using a second degraded characteristic of the circuit obtained according to a second degradation option. In exemplary embodiments, the first and second degradation options are selected from among an absolute-from-breakdown option, a unity-slope option, and a normalized intersection option.
A second aspect of the invention relates to computer program products for constraint characterization. In one embodiment of the invention, a computer program product includes a computer application adapted for processing by a computer. The computer application causes the computer to characterize first and second constraints of a circuit according to a model of an operation of the circuit to select a value for the first and second constraints, respectively. The computer application also causes the computer to modify the values selected for the first and second constraints to obtain optimized values for the first and second constraints, respectively. The optimized values of the first and second constraints avoid an invalid region of operation of the circuit.
In another embodiment, a computer application, adapted for processing by a computer, causes the computer to characterize first and second constraints of an electronic circuit according to a model of an operation of the circuit to acquire values for the first and second constraints, respectively. The second constraint is characterized independently of the characterization of the first constraint. The computer application further causes the computer to obtain optimized values of the first and second constraints, by optimizing the values acquired for the first and second constraints, respectively, so as to avoid an invalid meta-stable region of operation of the circuit.
More specifically, the application causes the computer to characterize the first and second constraints of the electronic circuit by using a first degraded characteristic of the circuit obtained according to a first degradation option, and by using a second degraded characteristic of the circuit obtained according to a second degradation option, respectively. In exemplary embodiments, the first and the second degradation options are selected from among an absolute-from-breakdown option, a unity-slope option, and a normalized intersection option.
A third aspect of the invention relates to methods for characterizing circuits. In one embodiment of the invention, a method for circuit characterization includes characterizing a first constraint of a circuit according to a model of an operation of the circuit to select a value for the first constraint. The method further includes characterizing a second constraint of the circuit according to the model of the operation of the circuit to select a value for the second constraint. The method modifies the values selected for the first and second constraints to obtain optimized values for the first and second constraints, respectively, so as to avoid an invalid region of operation of the circuit.
In another embodiment, a method of characterizing an electronic circuit includes characterizing first and second constraints of the circuit to acquire values for the first and second constraints, respectively. The second constraint is characterized independently of the characterization of the first constraint. The method further includes obtaining optimized values of the first and second constraints, by optimizing the values acquired for the first and second constraints, respectively, so as to avoid an invalid meta-stable region of operation of the circuit.
More specifically, the method includes characterizing the first constraint by using a first degraded characteristic of the electronic circuit obtained according to a first degradation option. The method further includes characterizing the second constraint by using a second degraded characteristic of the circuit obtained according to a second degradation option. In exemplary embodiments, the method includes selecting the first and second degradation options from among an absolute-from-breakdown option, a
Howick, Jr. E. Keith
Rao Guruprasad G.
O'Keefe Egan & Peterman, LLP
Silicon Metrics Corporation
Tran M.
LandOfFree
Apparatus for optimized constraint characterization with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for optimized constraint characterization with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for optimized constraint characterization with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3124551