Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-06-27
2001-03-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06202193
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for optimization of circuit design after an initial layout design, has been completed, in circuit design for integrated circuits and printed circuit boards.
DESCRIPTION OF THE RELATED ARTS
In the conventional circuit design of the integrated circuits and printed circuit boards, placement and routing of circuit elements and logic elements have been made by initial layout tools before local modifications to the placement and routing of circuit elements and logic elements are made in order to improve circuit performances or scale down the circuits by an optimization apparatus. On the basis of layout results, placement of cells and routings, interconnection length, interconnection capacitance and interconnection resistance are inputted into the circuit optimizing apparatus so that the optimization apparatus calculates accurate delay and powers of the circuits from the inputted informations for optimization.
FIGS. 1A and 1B
are circuit layouts for first and second conventional optimization methods for reducing circuit delay. In
FIG. 1A
, a small cell
501
is connected through interconnections
510
to cells
502
,
503
,
504
,
505
for driving the same. If the cell
501
for driving a large load has a small driving ability, then a large delay is caused. In this case, the cell
501
having the small driving ability is replaced by another cell
506
which has a higher driving ability but logically equivalent to the former cell
501
so as to reduce the circuit delay. If, however, the cell
501
has a sufficiently large driving ability for driving the cells
502
,
503
,
504
,
505
, then the cell
501
is replaced by other cell which has a lower driving ability but suitable for driving the cells
502
,
503
,
504
,
505
for scaling down the circuits, resulting in reduction of power consumption. This measurement is called as cell resizing.
The cell resizing comprises only replacement of the cells without changing and modifying the placement of the cells and routing of the interconnections between the cells. In most cases, the optimization of the circuit design can be achieved by simply applying the cell resizing to the circuit of which the layout has been made, for example, by replacing the cells with other cells without changing or modifying the placement and routing of the circuit design.
In
FIG. 2
, a buffer
601
is added in the circuit illustrated in FIG.
1
A. The buffer divides the load driven by the cell
501
into three divided loads and also divides a long interconnection into two divided interconnections. This measurement is called as buffer insertion.
If the buffer is added on or near the original interconnection with substantially no change to the routing, the desired improvement in delay of the circuit can be obtained. Even if the addition of the buffer results in an increase in the total length of he routing of the circuit, then the circuit delay is improved provided the effects of the load division and interconnection division exceed the influence due to the increase in total length of the routing.
FIG. 3
is a flow chart of the conventional optimization processes which is disclosed in 31st ACM/IEEE Design Automation Conference, 1994 pp. 327-332. First, an initial logic synthesis
701
is carried out before an initial cell placement
702
of the logic-synthesized circuits is then made. Optimization
703
of the circuits is made based upon the results of the initial cell placement
702
for satisfying the circuit requirement for subsequent cell replacement
704
in accordance with the optimization. If the circuit requirement is not yet satisfied, then the processes returns to the further optimization
703
and subsequent cell replacement
704
in accordance with the further optimization
703
. Only if all requirements are satisfied, routing process
705
is first made for routing interconnections between the cells. Layout information
710
includes layout information such as cell placements, interconnection routing, interconnection length, interconnection capacitance, and interconnection resistance which are referred by the initial cell placement
702
, the optimization
703
, the cell replacement
704
and the routing process
705
. A circuit modifying information
711
includes information about modifications of routing of the interconnections made in the optimization process and prepared by the optimization process and referred by the cell replacement
704
. A cell placement restriction information
72
includes information about placement restriction informations given by the optimization and referred by the cell replacement
704
.
The subsequent descriptions focus on the optimization
703
and subsequent cell replacement process
704
where local modifications such as the buffer insertion and the cell resizing are made for satisfying the circuit restriction requirement.
In the buffer insertion, since no routing of the interconnections has yet been made at this stage, a minimal spanning tree is prepared based upon the cell placement information. The buffer is placed at the nodes or near the terminals thereof The minimal spanning tree is a spanning tree being minimum in total length during any spanning trees. The routing delay is calculated by presumption of the minimal spanning tree as the actual routing.
FIG. 4
is a view of the minimal spanning tree of the placed cells. Cells
801
,
802
,
803
,
804
,
805
are placed at terminals of the minimal spanning tree. The minimal spanning tree has nodes
810
and
811
. The buffer is inserted at the terminals or nodes, for which reason the positional restriction of the buffer is supplied to the cell replacement
704
so that the cell replacement
704
tries to place the buffer at the restricted positions possibly.
FIG. 5
is another flow chart of the conventional optimization processes which is disclosed in the Japanese laid-open patent publication No. 5-114006.
First, an initial logic synthesis
901
is carried out before an initial layout
902
of the logic-synthesized circuits is then made. Optimization
903
of the circuits is made based upon the results of the initial layout
902
for satisfying the circuit requirement for subsequent relayout
904
in accordance with the optimization. If the circuit requirement is not yet satisfied, then the processes returns to the further optimization
903
and subsequent relayout
904
in accordance with the further optimization
903
. Layout information
910
includes layout information such as cell placements. interconnection routing, interconnection length, interconnection capacitance, and interconnection resistance which are referred by the initial relayout
902
, the optimization
903
, and the relayout
904
. A circuit modifying information
911
includes information about modifications of routing of the interconnections made in the optimization process and prepared by the optimization process and referred by the relayout
904
.
The subsequent descriptions focus on the optimization
903
and subsequent relayout process
904
.
In the optimization process
903
, new nets are added in the circuit without changing the circuit operations and in place redundancy nets are removed. Those processes are repeated, provided that the number of nets to be deleted is kept larger than the number of nets to be added. The cell placement information based on the layout by the initial layout
902
is used to inhibit addition of the net which may prevent post-replacement and routing by the relayout
902
. If, for example, a distance of the net connecting cells exceeds a predetermined maximum value, this net addition is inhibited.
In the relayout
904
, modification or change of layout is made by using spaced region which has been generated by deleting interconnections or cells in the optimization process
903
.
The first conventional optimization of the circuit design has the following disadvantages. In the optimization process
703
, the actual routing of the interconnections has not yet been made, for which
Emura Hideyuki
Sato Koichi
Kik Phallaka
NEC Corporation
Smith Matthew
Young & Thompson
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