Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-12-28
2010-10-12
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S082000, C326S086000
Reexamination Certificate
active
07812632
ABSTRACT:
The apparatus for on-die termination of a semiconductor memory includes a first ODT (On-Die Termination) voltage generating unit that outputs a first line voltage by calibrating an input voltage with a resistance ratio according to a first code having at least two bits; a first code calibrating unit that counts the first code according to the result of a comparison between the first line voltage and a reference voltage, stops the code count when the first code reaches a maximum value or a minimum value, and stores a code value based on a final count; a second ODT voltage generating unit that outputs a second line voltage by calibrating an input voltage with a resistance ratio according to the first code and a second code having at least two bits; and a second code calibrating unit that counts the second code according to the result of a comparison between the second line voltage and the reference voltage, stops the code count when the second code reaches the maximum value or the minimum value, and stores a code value based on a final count.
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Cho James H.
Hynix / Semiconductor Inc.
Kaminski Jeffri A.
Lo Christopher
Venable LLP
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