Apparatus for multiplying real-time 2's complement code in a dig

Details Apparatus for multiplying real-time 2's complement code in a dig Apparatus for multiplying real-time 2's complement code in a dig

1990-06-20

1993-01-19

Mai, Tan V.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

051811847

ABSTRACT:
A pipeline multiplier capable of multiplying 2's complement codes is disclosed. The multiplier operates the multiplication faster than the conventional one by receiving a first predetermined-bit of a multiplier and a second predetermined-bit of multiplicand; producing a multiplier multiplied by sequentially from a least significant bit (LSB) for the times of the second predetermined-bit numbers; logically ORing a most significant bit (MSB) of a preceding partial sum with a MSB of a present partial sum so as to correct the partial sums; and subtracting output of a last partial sum from a value produced by logically NANDing the multiplier and the MSB of the second predetermined-bit of the multiplicand.

REFERENCES:
patent: 3956622 (1976-05-01), Lyon
patent: 4736335 (1988-04-01), Barkan
patent: 4761756 (1988-08-01), Lee et al.

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