Electrical computers and digital data processing systems: input/ – Input/output data processing
Reexamination Certificate
1999-02-04
2002-04-09
Lee, Thomas (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
C710S002000, C710S100000
Reexamination Certificate
active
06370593
ABSTRACT:
TECHNICAL FIELD
This invention relates to computer system architecture, and, more particularly, to an apparatus for coupling signals between a processor bus and peripheral devices that do not use the same data transfer protocol.
BACKGROUND OF THE INVENTION
Continual advances are being made in a microprocessor technology to push the performance of personal computers to increasingly higher levels. These advances have resulted in an increased amount of data being transferred between the computer's central processor and a wide variety of peripheral devices. With this increased volume of data transfer has come the need for faster transfers of data between the processor and peripheral devices. Faster data transfer rates have resulted from continuous improvements in the manner in which data are transferred between the processor and the peripheral devices.
Devices normally communicate with the processor through an input/output “IO” bus. An early expansion bus, known as an Industry Standard Architecture (“ISA”) bus, satisfied the need for high-speed data transfer for many years. An extension to the ISA bus, known as an “EISA” bus was subsequently developed. Another bus architecture, known as Micro-Channel bus architecture, was also developed to provide high speed data transfer. Eventually, the IO demands of new computer systems exceeded the IO bandwidth limits of these bus architectures, making the IO bus a system throughput bottleneck. To resolve this bottleneck, a higher speed IO buses was developed, most recently the Peripheral Component Interconnect (“PCI”) bus architecture. However, PCI bus architecture has not yet completely replaced these earlier bus architectures because many presently available peripheral devices are unable to interface with a PCI bus. This is particularly true for relatively low speed peripheral devices, such as keyboards. As a result, state of the art computer systems continue to include these early bus designs, which are known as “legacy” buses. The continued use of legacy buses also results from the requirement that computer systems be “backward compatible” so that they can interface with peripheral devices, known as “legacy” devices, designed for older computer architectures as well as peripheral devices designed for state-of-the-art computer architectures. The same factors that dictate the continued use of these earlier bus designs also dictate the continued use of other legacy bus formats, interfaces, and devices, such as Integrated Device Electronics (“IDE”) buses and interfaces that are commonly used to interface processors to IDE disk drives. The term “legacy bus” is intended to encompass all of these ISA buses, EISA buses, Micro-Channel buses, IDE buses, and other pre-PCI buses.
As a result of the continuing need to interface with legacy devices, currently available computer systems generally include a PCI bus to provide high data transfer rates between the processor and peripheral devices, and a legacy bus, such as an ISA bus, to allow the processor to interface with relatively low speed peripheral devices and peripheral devices that are not yet capable of coupling to the PCI bus. A computer system
10
using conventional personal computer architecture is illustrated in FIG.
1
. The computer system
10
includes one or more central processors
12
a,b,
which may be microprocessors such as Pentium II® microprocessors sold by Intel Corporation. The processors
12
are each coupled to a processor bus
14
, which, as it well-known in the art, includes an address bus, a data bus, and a control/status bus. The processor bus
14
is coupled to a Processor/PCI bus bridge
16
, which is also sometimes known as a “North Bridge.” The bus bridge
16
couples the processor bus
14
to an IO bus, such as a PCI bus
18
. The bus bridge
16
also couples the processor
12
to a system memory device
20
through a memory bus
22
. The memory device
20
may be, for example, a dynamic random access memory (“DRAM”). Finally, the bus bridge
16
couples the processor
12
to various other devices (not shown), such as a graphics accelerators, a USB, or a network interface.
The PCI bus
18
is coupled to various internal PCI devices
26
and to internal PCI connectors
28
that may be coupled to various external PCI devices (not shown). The PCI bus
18
, which is a relatively high-speed bus, is also coupled to a relatively low speed legacy bus
24
through a PCI/Legacy bus bridge
30
, which is also sometimes known as a “South Bridge.” The bus bridge
30
also couples the PCI bus
18
to a mass storage device, such as a disk drive
32
, through an IDE bus
34
. For this purpose, the bus bridge
30
includes an IDE disk controller (not shown). Various relatively slow speed peripheral devices are coupled to the legacy bus
24
. Internal legacy devices
40
are coupled directly to the legacy bus
24
while external legacy devices (not shown) are coupled through legacy connectors
42
. The ISA bus
24
may also be coupled to various user interface devices (not shown), such as a floppy disk drive, a serial port, a parallel port, a mouse, and a keyboard, through a conventional input/output (“IO”) integrated circuit
46
.
The Processor/PCI bus bridge
16
is shown in greater detail in FIG.
2
. The bridge
16
includes a processor interface
50
that is coupled to the processor bus
14
, a memory interface
52
that is coupled to the memory bus
22
, a PCI interface
54
that is coupled to the PCI bus
18
, and non-PCI interfaces
56
that are coupled to other peripheral devices, as explained above with reference to FIG.
1
. The bus bridge
16
also includes a configuration register
58
that is programmed during initialization with various parameters to control the operation of the bus bridge
16
. The structure and operation of the interfaces
50
-
56
, as well as the manner in which they interact with each other, are well-known to one skilled in the art. Therefore, further description of these conventional aspects of the bus bridge
16
will be omitted in the interest of brevity.
The computer system
10
shown in
FIG. 1
, in the past, achieved satisfactory performance. However, with the increasing need for ever faster computer systems, the relatively low speed of the legacy bus
24
has slowed the data transfer rates to and from peripheral devices coupled to the legacy bus
24
to unacceptably slow levels. As a result, peripheral devices formerly coupled to the legacy bus
24
are increasingly being coupled to the PCI bus
18
. It would also be desirable to couple devices that are now coupled to the PCI/Legacy bus bridge
30
, such as the IDE bus
34
and the disk drive
32
, to the Processor/PCI bus bridge
16
, thereby saving the time needed to couple signals through the PCI bus
18
and PCI/Legacy bus bridge
30
. Coupling these devices to the PCI bus
18
rather than the legacy bus
24
would also allow elimination of the legacy bus
24
and associated circuitry thereby reducing the cost of computer systems. However, coupling peripheral device that are not designed to interface with a PCI bus (referred to as “non-PCI devices) presents a number of problems that would appear to be difficult to overcome. For example, moving the IDE disk controller for the disk drive
32
from the PCI/Legacy bus bridge
30
to the Processor/PCI bus bridge
16
would necessitate adding a large number of connector terminals or “pins” to the bus bridge
16
. However, the number and density of connector pins in the PCI bus bridge
16
is, many cases, already approaching the maximum limits of what is possible with conventional technology. As a result, it has become increasingly difficult to relocate peripheral devices from slower speed buses to higher speed buses or higher speed bus bridges.
SUMMARY OF THE INVENTION
In accordance with the present invention, a relatively high-speed bus, such as a PCI bus, is used to interface a processor to peripheral devices specifically adapted to the high-speed bus. A subset of signal lines of the high-speed bus is also used to interface the processor
Dorsey & Whitney LLP
Lee Thomas
Mai Rijue
Micro)n Technology, Inc.
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