Apparatus for memory bus tuning and methods therefor

Details Apparatus for memory bus tuning and methods therefor Apparatus for memory bus tuning and methods therefor

1998-10-02

2002-12-17

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C709S241000

Reexamination Certificate

active

06496911

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to memory bus tuning in data processing systems having variable numbers of dynamic memory modules.
BACKGROUND INFORMATION
High-speed data processing systems employing buffered synchronous dynamic random access memory (SDRAM) have a tightly constrained timing budget. Buffered SDRAM include an on-chip buffer to redrive the control signals. This SDRAM may be operated either in buffer mode or in register mode. In register mode, control signals, such as row address strobe (RAS), column address strobe (CAS), and read/write (R/W) control are latched for one clock cycle. In this way, register mode SDRAM avoid control signal set-up time constraints, but pay a one clock cycle penalty. Conversely, SDRAM operating in buffer mode avoid the one-cycle penalty but must satisfy control signal set-up time requirements.
As memory cycle times decrease, that is, as memory speed increases, set-up time requirements become increasingly stringent. For example, in a data processing system having a memory bus operating at approximately 83 megahertz (MHz), the memory cycle time is 12 nanoseconds (ns). With a typical SDRAM dual inline memory module (DIMM) requiring a 7 ns control signal set-up time, and a 2 ns data bus hold time, only a 3 ns design margin remains.
In a data processing system having variable numbers of DIMMs, the changing load condition presented thereby may substantially exhaust the design margin. This may be understood by referring to
FIG. 1
, illustrating an SDRAM timing diagram. In SDRAM, memory activity is synchronized to clock signal
102
. The memory cycle time is determined by the clock period, T
p
, which in the example discussed above is approximately 12 ns, corresponding to a clock frequency of approximately 83 MHz. Memory control signals
104
must be switched, that is, asserted, a specified minimum set-up time, T
su
, before the clock edge, T
1
, initiating the current memory cycle. If the control signals are asserted less than a set-up time prior to the clock edge, operation of the SDRAM may be unreliable.
Increased loading on the SDRAM control signal lines due to added SDRAM DIMMs increase the switching times of the control signals. This is illustrated by the dotted portion of control signals
104
illustrated in FIG.
1
. If the switching time of the control signals becomes too long, the set-up time criteria for the SDRAM will be violated, and the operation of the SDRAM will be compromised.
Additionally, proper operation of the SDRAM requires that data signals be held for a period of time, T
h
, after the clock edge, T
2
, latching the data. In a data processing system in which the number of SDRAM DIMMs is variable, increasing the number of DIMMs makes the hold time criteria easier to satisfy. Conversely, reducing the number of DIMMs reduces the hold time margin. If the hold time criteria is violated, capture of the data may fail.
Thus, there is a need in the art for apparatus and methods for tuning, or matching, the memory bus to varying load conditions, thereby maintaining control signal switching times within set-up time constraints while maintaining control signal wave shapes, and, additionally, preserving data signal hold times.
SUMMARY OF THE INVENTION
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, an apparatus for memory bus tuning, which includes a plurality of drivers coupled to the memory bus, wherein each driver has a selectable drive strength. At least one register operable for receiving a data value is also included, the selectable drive strength being selected in response to the data value, wherein the data is operable for setting in response to an amount of memory coupled to the memory bus.
There is also provided, in a second form, a data processing system including a central processing unit (CPU), a memory device coupled to the CPU via a memory bus, and an apparatus for tuning the memory bus. The apparatus for tuning the memory bus includes a plurality of drivers coupled to the memory bus, wherein each driver has a selectable drive strength, and at least one register operable for receiving a data value from the CPU, the selectable drive strength being selected in response to the data value, the data being operable for setting in response to an amount of memory coupled to the memory bus.
Additionally there is provided, in a third form, a method of memory bus tuning. The method includes the steps of determining an amount of memory in a memory device coupled to the memory bus, setting a first data value in a first register in response to the amount of memory, and selecting a drive strength of a plurality of drivers operable for driving the memory bus in response to the first data value.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 5625580 (1997-04-01), Read et al.
patent: 5727182 (1998-03-01), Fukushima et al.
patent: 5752066 (1998-05-01), Bealkowski et al.
patent: 5768584 (1998-06-01), MacDonald et al.
patent: 6067650 (2000-05-01), Beausang et al.

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