Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-12-27
2009-08-18
Cho, James (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S016000
Reexamination Certificate
active
07576560
ABSTRACT:
An apparatus for measuring an on-die termination (ODT) resistance includes an ODT controller and a driver. The ODT controller receives a plurality of decoding signals, a first test mode signal, and a second test mode signal to generate a plurality of pull-up signals and a plurality of pull-down signals. The pull-up signals are enabled in response to the decoding signals and the first test mode signal, and the pull-down signals are enabled in response to the decoding signals and the second test mode signal. The driver receives the pull-up signals and the pull-down signals to drive a data terminal. At least one of the decoding signals is enabled by a mode register set (MRS) for setting an ODT mode.
REFERENCES:
patent: 6909305 (2005-06-01), Li et al.
patent: 6922074 (2005-07-01), Coughlin et al.
patent: 7372294 (2008-05-01), Kim
patent: 7421631 (2008-09-01), Morioka
patent: 10-2007-0036552 (2007-04-01), None
Cho James
Cooper & Dunham LLP
Hynix / Semiconductor Inc.
White John P.
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