Apparatus for masked arbitration between masters and...

Details Apparatus for masked arbitration between masters and... Apparatus for masked arbitration between masters and...

2011-07-12

2011-07-12

Misiura, Brian T (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S028000, C710S036000, C710S240000, C710S243000

Reexamination Certificate

active

07979615

ABSTRACT:
An apparatus is disclosed for handling multiple requestors desiring access to a resource. The apparatus includes a plurality of masters and a plurality of arbitrators. Each arbitrator is assigned to a different one of the plurality of masters. Also, each arbitrator is defined to consider a different portion of the multiple requestors when selecting a requestor to be serviced by the master to which the arbitrator is assigned. Each arbitrator is further defined to select a requestor from the different portion of the multiple requestors, such that selection of a particular requestor is not duplicated among the plurality of arbitrators. Additionally, requestor selection by each of the plurality of arbitrators is performed in a same clock cycle.

REFERENCES:
patent: 6859852 (2005-02-01), Jahnke et al.
patent: 6976109 (2005-12-01), Shenderovich
patent: 7051133 (2006-05-01), Takata
patent: 7051135 (2006-05-01), Zhu
patent: 7120714 (2006-10-01), O'Connor et al.
Computers Without Clocks—taken from Scientific American—Aug. 2002—11 pages.
Clockless Chips—taken from Technology Review—Oct. 2001—7 pages.

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