Coating apparatus – Gas or vapor deposition
Patent
1992-12-22
1994-05-24
Chaudhuri, Olik
Coating apparatus
Gas or vapor deposition
414935, 414941, 29 2501, 437925, 118725, 118729, C23C 1600
Patent
active
053145380
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to an apparatus and method for manufacturing a semiconductor device of the type referred to as a multistep process and apparatus which are capable of forming a single layer film and a multilayer film having improved film quality by performing different types of processings continuously without having the wafer exposed to the ambient air.
PRIOR ART
In apparatus for manufacturing a very large integrated circuit (VLSI) semiconductor device, apparatus providing for performance of several process steps continuously without having the semiconductor device exposed to the ambient air has become the trend in recent years, thus making it possible to aim at improvement of the film quality of a formed film and the like and improvement of adhesion among multiple layers of the film. As the combination of process steps, for example, film formation and etch back after film formation, processing before oxidation and formation of an oxide film, and continuous formation of a barrier metal film/a metal film may be mentioned.
As representative apparatus for manufacturing a semiconductor device capable of such processing, there are what is called a multi-chamber process apparatus using multi-chambers, a multistep process apparatus and a cluster apparatus in which respective processing sections are arranged in close vicinity to one another and the like.
FIG. 10 is a block diagram showing an apparatus for manufacturing a semiconductor device in which an insulating film is formed on a wafer by performing different types of process steps continuously using conventional multi-chambers.
In FIG. 10, a reference numeral 1 represents a cassette chamber for preparing to carry a wafer into and out of the multi-chambers, 3 represents a load-lock chamber for adjusting the pressure between chambers upon entry and exit of the wafer, 7a represents a valve for opening and closing communication between the cassette chamber 1 and the load-lock chamber 3, 4 represents a buffer chamber where a robot 5 for carrying the wafer is installed, 7b is a valve for opening and closing communication between the load-lock chamber 3 and the buffer chamber 4, and 6a to 6e represent processing chambers arranged radially with respect to the buffer chamber 4 as the center. They are used for the purposes described hereunder. For example:
(1) the processing chamber 6a is used for forming a SiO.sub.2 film (film formation temperature at 400.degree. C.) by a plasma chemical vapor deposition (CVD) method;
(2) the processing chamber 6b is used for forming a PSG film (film formation temperature at 400.degree. C.) by a low pressure CVD method;
(3) the processing chamber 6c is used for etching back (at room temperature) of a formed film;
(4) the processing chamber 6d is used for forming a Si.sub.3 N.sub.4 film (film formation temperature at 400.degree. C.) by a plasma CVD method; and
(5) the processing chamber 6e is used for forming a SiO.sub.2 film (film formation temperature at 400.degree. C.) by a low pressure CVD method. Moreover, heaters (not illustrated) for maintaining a wafer 9 at the film formation temperature are provided in respective processing chambers 6a to 6e. Further, 8a to 8e represent valves for opening and closing the ports providing communication between the buffer chamber 4 and respective processing chambers 6a to 6e. In addition, 2 represents a robot for delivering the wafer 9 from the cassette chamber 1 to a robot (not illustrated) provided in the load-lock chamber 3.
When a flat multi-layer insulating film composed of SiO.sub.2 film/PSG film is formed using the above-described apparatus, the wafer 9 moves among the chambers as described hereunder. Namely, the robot 5 carries the wafer 9 into and out of respective processing chambers 6a, 6b and 6c so that respective processes are performed in the order of the processing chamber 6a/the processing chamber 6b/the processing chamber 6c.
The heaters for heating and maintaining the wafer 9 at the film formation temperature are provided in respective pr
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patent: 4846623 (1989-07-01), Otani et al.
patent: 5067218 (1991-11-01), Williams
patent: 5118642 (1992-06-01), Yoshino et al.
patent: 5174827 (1992-12-01), Misiano et al.
patent: 5174881 (1992-12-01), Iwasaki et al.
Maeda Kazuo
Nishimoto Yuhko
Tokumasu Noboru
Alcan Tech Co., Inc.
Booth Richard A.
Canon Sales Co., Inc.
Chaudhuri Olik
Semiconductor Process Laboratory
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