Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-01-21
2001-07-17
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06263389
ABSTRACT:
This application is related to, and incorporates by reference, an application titled “A Method for Operating a Host Bus” filed on even date herewith, Ser. No. 09/010,084, now U.S. Pat. No. 6,041,380.
1. FIELD OF THE INVENTION
The present invention relates to computer systems. More particularly, the present invention relates to apparatus and methods for increasing the loads supportable on the host bus of a computer system.
2. BACKGROUND OF THE INVENTION
In many computer systems, there are limits to the number of bus agents that may be operably connected to the host bus if the host bus is to be clocked at a certain frequency. These limits result from the capacitance and distributed resistance physically present on chips. For example, as shown in the example prior art system of
FIG. 4
, in Pentium® Pro based computer systems, the host or P6 bus is limited to 4 Pentium® Pro processors and 1 bus bridge or system controller if the P6 bus is to be clocked at 100 MHz. If the P6 bus is operably connected to 4 processors and 4 system controllers, the clock rate of the P6 bus must be decreased to 66 MHz. Such a decrease in the P6 clock rate results in lower bus bandwidth and thus, a slower and relatively more inefficient computer system, having decreased system throughput. Alternatively, if added loads are desired for a computer system, these must be placed on a bus that is connected to the bus bridge, placing them a further level away from the processor. This leads to latency problems for these loads. While such problems are less of an issue in a single processor system, in systems that require multiple processors and have many attached network cards or other peripherals, the load limits represent significant obstacles or undesirable trade-offs.
Thus, there exists a need in the art for methods and apparatus for increasing the number of devices operably connected to a host bus when clocking the bus a certain frequency.
3. SUMMARY OF THE INVENTION
The present invention comprises a computer system having a host bus comprising a first bus following a protocol, a second bus following the protocol and linking logic operably connecting the first and second buses such that the host bus follows the protocol. The present invention may further comprise at least one system controller operably connected to the second bus and at least one peripheral device operably connected to the system controller, wherein the early snoop signal is asserted by the system controller.
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patent: 5734850 (1998-03-01), Kenny et al.
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patent: 6041380 (2000-03-01), LaBerge
Beausoleil Robert
Chung-Trans X.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
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