Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2005-05-03
2005-05-03
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S401000, C713S600000
Reexamination Certificate
active
06889336
ABSTRACT:
A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffered clock signal and generates a delayed clock signal, and an output circuit including output signal paths for outputting the output signals synchronously with the system clock signal by using the delayed clock signal. At least one of the output signal paths includes a delay circuit and an output buffer. Each delay circuit provides a programmable delay to the delayed clock signal to generate a unique delayed clock signal used to clock an output signal into the respective output buffer. By programming the delays based upon output skew, the output skew can be improved.
REFERENCES:
patent: 4949361 (1990-08-01), Jackson
patent: 5398262 (1995-03-01), Ahuja
patent: 5414381 (1995-05-01), Nelson et al.
patent: 5692165 (1997-11-01), Jeddeloh et al.
patent: 5812462 (1998-09-01), Merritt
patent: 5819076 (1998-10-01), Jeddeloh et al.
patent: 5852378 (1998-12-01), Keeth
patent: 5857095 (1999-01-01), Jeddeloh et al.
patent: 5875134 (1999-02-01), Cloud
patent: 5886948 (1999-03-01), Ryan
patent: 5903747 (1999-05-01), Casal
patent: 5920518 (1999-07-01), Harrison et al.
patent: 5923611 (1999-07-01), Ryan
patent: 5930198 (1999-07-01), Ryan
patent: 5936893 (1999-08-01), Merritt
patent: 5986948 (1999-11-01), Cloud
patent: 6026051 (2000-02-01), Keeth et al.
patent: 6069506 (2000-05-01), Miller, Jr. et al.
patent: 6069510 (2000-05-01), Keeth
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6104209 (2000-08-01), Keeth et al.
patent: 6104643 (2000-08-01), Merritt
patent: 6111446 (2000-08-01), Keeth
patent: 6137334 (2000-10-01), Miller, Jr. et al.
patent: 6141292 (2000-10-01), Lee et al.
patent: 6167528 (2000-12-01), Arcoleo
patent: 6240042 (2001-05-01), Li
patent: 6243797 (2001-06-01), Merritt
patent: 6256260 (2001-07-01), Shim et al.
patent: 6340905 (2002-01-01), Schultz
patent: 6469550 (2002-10-01), Kurd
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6570428 (2003-05-01), Liao et al.
patent: 6598171 (2003-07-01), Farmwald et al.
patent: 6704881 (2004-03-01), Li et al.
patent: 6779097 (2004-08-01), Gillingham et al.
patent: 6-349946 (1994-12-01), None
“DDR SDRAM Functionality and Controller Read Data Capture”,DesignLine, vol. 8, Issue 3, 3Q99, Micron Technology, Inc., pp. 1-24, (1999).
“Double Data Rate (DDR) Sdram”,Micron Semiconductor Products, Inc., 64Mb: x4, x8, x16 DDR SDRAM,pp. 1-66, (2000).
Mikhalev Vladimir
Schoenfeld Aaron M.
Cao Chun
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Apparatus for improving output skew for synchronous... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for improving output skew for synchronous..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for improving output skew for synchronous... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3444723