Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-28
2009-06-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07543257
ABSTRACT:
An apparatus for giving assistance in analyzing deficiency in a RTL-input program, includes a partial RTL creator which creates partial RTL description data containing logic description identical with logic description extracted from successive portions of input RTL description data, and having correspondence in signals identical with the same in the input RTL description data, an estimator which receives the partial RTL description data to execute a RTL-input program, and creates error-judgment data indicative of whether the RTL-input program contains deficiency, and an execution controller which controls a volume of logic description contained in partial RTL description data to be next created by the partial RTL creator, based on the error-judgment data, and outputs partial RTL description data causing the same deficiency as deficiency of the input RTL description data, and having a minimum volume of logic description.
REFERENCES:
patent: 2004/0049753 (2004-03-01), Kabuo
patent: 2005/0055612 (2005-03-01), Yamada
patent: 5-242191 (1993-09-01), None
patent: 11-102385 (1999-04-01), None
patent: 2003-085220 (2003-03-01), None
Foley & Lardner LLP
NEC Corporation
Siek Vuthe
LandOfFree
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