Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1998-12-02
2001-06-26
Shalwala, Bipin (Department: 2673)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S600000
Reexamination Certificate
active
06253332
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic systems utilizing clock signals. More particularly, the present invention provides a method and apparatus for shifting the voltage level and swing of clock pulses.
2. The Background Art
Modern electronic systems, especially computer systems, utilize clock signals to provide timing synchronization to the various devices present in the system.
Clock signals that are only used internal to a given device are usually supplied within that device by a clock source of some sort. Other clock signals are provided by the system in order to ensure that devices within the system are synchronized by receiving the same signal transitions at the same time. Often these system-supplied clock signals are used internally within a given system device, rather than the device supplying an independent clock signal.
FIG. 1
is a block diagram showing various computer components and their relation to a system-provided clock.
Referring to
FIG. 1
, a computer
10
comprises a power supply
12
, memory cards
14
, removable circuit card assemblies (CCA's)
16
a,
16
b,
16
c,
and
16
d,
other devices
18
, and clock source
20
. CCA's
16
a,
16
b,
16
c,
and
16
d
may comprise video devices, audio devices, ethernet devices, or any other type of assembly that requires access to a common bus that is present within the system.
Individual ones of CCA's
16
a,
16
b,
16
c,
and
16
d
may or may not require an outside system clock. In the event that access to the system clock is required, it is provided to a given one of CCA's
16
a,
16
b,
16
c,
and
16
d
through the proper ones of connector interfaces
22
a,
22
b,
22
c,
and
22
d
respectively, depending on which of CCA's
16
a,
16
b,
16
c,
and
16
d
require access to the system clock.
FIG. 2
is a schematic diagram depicting a prior art CCA.
Referring to
FIG. 2
, CCA
16
comprises a system clock source
20
, the output of which passes through connector interface
22
to clock device
24
which buffers the incoming clock signal and provides it to processor
26
, memory
28
, buffer
30
, and other devices
32
, CCA components which are representative of what may or may not be on a given plug-in card in a given computer.
Although the providing of a system clock signal to CCA-level components is desirable for many reasons, problems arise when the level of technology increases faster than hardware is replaced. Motherboards which are designed and manufactured using one level of technology, and CCA's designed and manufactured using a later technology may have incompatible clock signal levels, causing critical malfunctions.
One possible incompatibility between clock signals is the voltage level used, and the voltage swing between transitions from low to high, and from high to low. Later technology typically operates at lower voltage levels than earlier technology. Thus a CCA made with a later technology than contained on the motherboard will often require lower clock signal levels than which are present on the motherboard. The requirement of the lower clock signal levels on the CCA as compared to the motherboard makes it necessary for CCA designers to take into account the higher incoming voltage levels, and compensate in some way on the CCA so as to prevent critical malfunctions and to prevent possible damage to CCA components.
A prior art solution which decreases the magnitude of incoming clock signals involves putting capacitors such as capacitors
34
a
through
34
f
in series with the clock signal paths.
This prior art solution provides a maximum signal level that is within the magnitude desired by the new technology logic, but which has several drawbacks.
First, although the maximum incoming clock signal voltage is reduced for use on a CCA by adding capacitors in series with the signal path, the voltage swing between a “low” and a “high” is also comparatively reduced, significantly increasing the possibility that a low may be mistaken for a high, or that a high may be mistaken for a low.
Second, the prior art solution uses capacitors to solve the signal level problem. Capacitors inherently have very loose tolerances on their value when manufactured. Thus, the values of installed capacitors may significantly vary from CCA to CCA, and thus CCA's may vary from system to system in the way they respond to the converted clock signal levels.
Third, installing capacitors on CCA's requires the use of valuable board space, thus precluding the use of the space for other valuable purposes. In modern electronics, there is a strong desire to eliminate unnecessary components, leaving as much board space as possible for other, more desired uses.
OBJECTS AND ADVANTAGES OF THE INVENTION
It is an object and advantage of the present invention to provide a method and apparatus for reducing the maximum incoming clock signal level without reducing the voltage swing between a logical low and a logical high.
It is a further object and advantage of the present invention to provide a method and apparatus for reducing the maximum incoming clock signal level using components having predictable, tight tolerances.
It is yet a third object and advantage of the present invention to provide a method and apparatus for reducing the maximum incoming clock signal level, which maximizes the amount of CCA space available for other circuitry.
SUMMARY OF THE INVENTION
An apparatus for reducing the magnitude of a external clock signal is provided wherein the external clock signal is provided on the motherboard of a computer, the signal is provided onto a plug-in CCA, and the signal must pass through a plurality of resistors prior to being provided to circuits requiring the reduced magnitude signal.
REFERENCES:
patent: 3688036 (1972-08-01), Bland
patent: 3922685 (1975-11-01), Opas
patent: 3932865 (1976-01-01), Sagara et al.
patent: 4497060 (1985-01-01), Yang
patent: 4587519 (1986-05-01), Munetsugu et al.
patent: 5589790 (1996-12-01), Allen
patent: 5732249 (1998-03-01), Masuda et al.
patent: 5900768 (1999-05-01), Price
patent: 6035358 (2000-03-01), Tanikawa
patent: 6065129 (2000-05-01), Sakamoto et al.
Patel Nitin
Shalwala Bipin
Sierra Patent Group Ltd.
Sun Microsystems
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