Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-06-28
2001-02-27
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S189090, C365S210130
Reexamination Certificate
active
06195281
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a nonvolatile ferroelectric semiconductor memory device using ferroelectric capacitor memory cell and more particularly, to a reference voltage generator to generate a reference voltage in a read operation of the nonvolatile ferroelectric semiconductor memory device.
DESCRIPTION OF THE PRIOR ART
Generally, a ferroelectric semiconductor memory device, e.g., a nonvolatile ferroelectric random access memory (NVFRAM) includes a plurality of memory cells. Each memory cell includes transistor and at least one ferroelectric capacitor so that the NVFRAM has characteristics of fast access time and small chip size.
FIG. 1
shows a hysteresis loop of a ferroelectric capacitor. That is, a relationship between the polarization charge Q and voltage V applied to the capacitor is shown in the FIG.
1
. In the ferroelectric capacitor, even if the voltage difference between two terminals of the ferroelectric capacitor is zero voltage, the charge Q may be one of two values of P
1
and P
2
, to thereby store binary data. Accordingly, based on this characteristics, the ferroelectric capacitor has been used in the nonvolatile memory device.
According to the variation of voltage applied to the both terminals of the ferroelectric capacitor, the stored charges therein vary with the degree of polarization of the ferroelectric material as shown in the hysteresis loop of FIG.
1
.
For example, it is assumed that the voltage level of −V
1
is applied to the two terminals of the ferroelectric capacitor, supposing that a state P
1
and a state P
2
stand for logic data “1” and “0” respectively. In this case, when the initial charge state of the ferroelectric capacitor is a state P
1
, the charge state thereof is moved to a state P
3
so that the variation of &Dgr;Q
1
is induced. When the initial charge state of the ferroelectric capacitor is a state P
2
, the charge state thereof is moved to a state P
3
so that the variation of the charge of &Dgr;Q
0
is induced. This varied charge &Dgr;Q
1
or &Dgr;Q
0
is charge-shared with a charge previously induced on a bit line of a selected memory cell, and the shared charge on the bit line is coupled to a sense amplifier which amplifies and outputs it as a sensed data corresponding thereto. A reference voltage is required to operate the sense amplifier, and has a mean value of combined varied charge, (&Dgr;Q
1
+&Dgr;Q
0
)/2. The reference voltage is generally generated by using a ferroelectric dummy cell circuit.
FIG. 2
shows a circuit diagram of a reference voltage generation circuit which is disclosed in an article by Hiroki Koike et al., “60 ns 1 M bit Nonvolatile Ferroelectric Memory with Non-driven Cell Plate Line Read/Write Scheme”, IEEE.
Journal of Solid State Circuits,
Vol.31, No.11, November 1996. As shown, two dummy cell circuits include two ferroelectric capacitors C
0
and C
1
, respectively. The ferroelectric capacitors C
0
and C
1
store the logic data “0” and “1” respectively. When turning on switching transistors T
0
and T
1
coupled to a dummy word line (DWL), the varied charges &Dgr;Q
0
and &Dgr;Q
1
are applied to a reference lines REF
1
and REF
2
respectively from the ferroelectric capacitors C
0
and C
1
. At this time, When a “high” state signal is applied to an equalizing dummy line EDL, a transistor T
2
turns on to thereby add &Dgr;Q
0
and &Dgr;Q
1
mentioned above, and when each transistor coupled to DTGN or DTGT is turned on, the charge of (&Dgr;Q
1
+&Dgr;Q
0
)/2 is applied to bit lines BL
1
N, BL
2
N or BL
1
T, BL
2
T.
However, since in the conventional reference voltage circuits, the two dummy cells should store “1” and “0” and at least one switching operation is required in order to provide the reference voltage for each access to a memory cell, the switching transistors constituting of the dummy cells may be easily fatigued to thereby cause some variation of the reference voltage. Furthermore, since the dummy cells are coupled to the bit line having a multiplicity of memory cells, the dummy cell is read out much more often than the memory cell. Thus, the problem is that lifetime of the device seriously depends upon an operation state of the dummy cell.
Also, another problem is that since the reference voltage generation circuit includes a complex extra circuit for driving the dummy cell which has the ferroelectric capacitor, the further integration of the semiconductor device may be limited.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an apparatus for generating a reference voltage in a ferroelectric memory device, which is capable of implementing a high integration in the ferroelectric memory device and effectively providing a reference voltage by using a linear capacitor.
It is another object of the present invention to provide an apparatus for generating a reference voltage in a ferroelectric memory device capable of increasing reliability of the ferroelectric memory device.
In accordance with an aspect of the present invention, there is provided an apparatus for generating a reference voltage in ferroelectric memory device including a sense amplifier which senses and amplifies voltage difference between a bit line and the bit line bar, and a plurality of memory cells, each having a ferroelectric capacitor, said apparatus comprising: a linear capacitor, in response to a predetermined voltage signal inputted from a cell plate line, for storing a predetermined amount of charges; a first switching device for selectively coupling the linear capacitor to the cell plate line; and a second switching device for selectively coupling the linear capacitor to the bit line to thereby provide the predetermined amount of charges as the reference voltage to the bit line.
In accordance with another aspect of the present invention, there is provided a ferroelectric memory device having a reference voltage generation circuit for generating a reference voltage, a sense amplifier which senses and amplifies voltage difference between a bit line and a bit line bar, and a plurality of memory cells, each having a ferroelectric capacitor, comprising: a linear capacitor, in response to a predetermined voltage signal inputted from a cell plate line, for storing a predetermined amount of charges; a first switching device for selectively coupling the linear capacitor to the cell plate line; and a second switching device for selectively coupling the linear capacitor to the bit line to provide thereby the predetermined amount of charges as the reference voltage to the bit line.
REFERENCES:
patent: 5600587 (1997-02-01), Koike
patent: 5615144 (1997-03-01), Kimura et al.
patent: 5844832 (1998-12-01), Kim
patent: 6025225 (2000-02-01), Forbes et al.
patent: 6026009 (2000-02-01), Choi et al.
patent: 6058049 (2000-05-01), Kye et al.
patent: 10069790 (1998-03-01), None
patent: 10289590 (1998-10-01), None
patent: 11086566 (1999-03-01), None
patent: 11232881 (1999-08-01), None
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
Le Vu A.
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