Apparatus for generating address bit patterns for testing semico

Details Apparatus for generating address bit patterns for testing semico Apparatus for generating address bit patterns for testing semico

1993-05-25

1995-12-19

Beausoliel, Jr., Robert W.

Static information storage and retrieval

Read/write circuit

Testing

G11C 700

Patent

active

054774942

ABSTRACT:
An apparatus for testing a semiconductor memory device even of such a complicated addressing scheme that column address allocation differs from one to another row address. Memory cells of the memory device can be accessed in a desired sequence by changing over the conditions for address translation on a real-time basis. A pattern generator generates a plurality of addresses. A plurality of address bit selector circuits select optionally the addresses outputted from the pattern generator on a bit-by-bit basis. A plurality of switching circuits are provided for changing over a plurality of selected addresses outputted from the address bit selector circuits on a real-time basis. A plurality of address translation/memory circuits are supplied with a plurality of the addresses changed over by the switching circuits. A memory incorporated in each of address translation/memory circuits is divided into a plurality of memory areas selectable on a real-time basis. With the selected addresses switched in response to an address switching signal supplied from the pattern generator, address translation data stored in the memory areas selected by the address switching signal are read out and supplied to the semiconductor memory device under test for accessing memory cells thereof.

REFERENCES:
patent: 4520453 (1985-06-01), Chow
patent: 4602368 (1986-07-01), Circello et al.
patent: 4964035 (1990-10-01), Aoyama et al.
patent: 5263029 (1993-11-01), Wickland, Jr.

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