Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-10-15
2002-05-14
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S240000, C710S052000
Reexamination Certificate
active
06389492
ABSTRACT:
RELATED APPLICATION
The subject matter of this application is related to the subject matter in a co-pending non-provisional application by the same inventor(s) as the instant application and filed on the same day as the instant application entitled, “Method for Flexibly Allocating Request/Grant Pins Between Multiple Bus Controllers,” having Ser. No. 09/418,468, and filing date Oct. 15, 1999.
BACKGROUND
1. Field of the Invention
The present invention relates to buses in computer systems. More particularly, the present invention relates to a system for flexibly allocating I/O pins used for bus request and bus grant signals between multiple bus controllers located on the same semiconductor chip.
2. Related Art
Much of the interconnection circuitry in a microprocessor-based computer system is typically aggregated in a “core logic” unit that couples the microprocessor to other parts of the computer system, such as a memory, a peripheral bus and a graphics controller. For reasons of cost, it is preferable to integrate the core logic unit into a single semiconductor chip. However, the I/O pin limitations on a single chip can present problems. For example, a single core logic chip that includes all of a computer system's interconnection circuitry may require interfaces for a processor bus, a memory bus, an AGP bus for a graphics controller and a PCI bus for peripheral devices. Providing I/O pins for all of these interfaces requires many hundreds of I/O pins, especially if the buses support 64 bit transfers. Given present semiconductor packaging technology, this I/O pin requirement can easily exceed the I/O pin limitations of a single semiconductor chip.
Note that many bus signals lines are not utilized well. In particular, some bus grant lines and bus request lines are not always needed. Recall that bus request lines are used by devices on the bus to request control of the bus from a bus arbiter in order to perform bus accesses. Bus grant lines are used by the bus arbiter to grant control of the bus to a requester. In a typical bus, such as the peripheral component interconnect (PCI) bus, there is one request line and one grant line for each master device on the bus. For example, the PCI bus supports up to seven bus request lines and seven bus grant lines for up to seven bus masters.
In order to conserve on the number of I/O pins used, a typical core logic chip provides a limited number of pins for request lines and grant lines. This limits the number of bus master devices that can be supported. Furthermore, the number of request and grant lines are typically fixed for each bus controller. This means that a typical core logic chip cannot be used in certain computer system configurations. For example, a given computer system configuration may require a particular allocation of request and grant lines between bus interfaces, whereas another computer system configuration may require a different allocation.
What is needed is a system for flexibly allocating I/O pins used for bus request and bus grant signals between multiple bus controllers located on the same semiconductor chip.
SUMMARY
One embodiment of the present invention provides an apparatus that flexibly allocates I/O pins used for bus grant signals between bus controllers. The apparatus includes a semiconductor chip containing a first bus arbitration circuit and a second bus arbitration circuit. A first set of grant lines originates from the first bus arbitration circuit and is used to grant control of a first bus to devices on the first bus. This first set of grant lines is divided into a first subset of grant lines and a second subset of grant lines. A second set of grant lines originates from the second bus arbitration circuit and is used to grant control of a second bus to devices on the second bus. This second set of grant lines is divided into a third subset of grant lines and a fourth subset of grant lines. A selector circuit selects a plurality of outputs from between the first subset of grant lines and the third subset of grant lines. This plurality of outputs is coupled to a first set of output pins on the semiconductor chip. The selector circuit is configured to select the first subset of grant lines to be driven through the first set of output pins during a first mode of operation, and is configured to select the third subset of grant lines to driven through the first set of output pins during a second mode of operation.
In one embodiment of the present invention, the second subset of grant lines is coupled to a second set of output pins, and the fourth subset of grant lines is coupled to a third set of output pins.
One embodiment of the present invention includes a set of request lines coupled to input pins of the semiconductor chip. This set of request lines is divided into a first subset of request lines, a second subset of request lines and a third subset of request lines. The first subset of request lines is coupled to the first bus arbitration circuit. The second subset of request lines is coupled to the second bus arbitration circuit. The third subset of request lines is coupled to both the first bus arbitration circuit and the second bus arbitration circuit. In a variation on this embodiment, a routing circuit is configured to route the third subset of request lines to the first bus arbitration circuit during the first mode of operation, and is configured to route the third subset of request lines to the second bus arbitration circuit during the second mode of operation.
One embodiment of the present invention includes a configuration register that indicates whether the selector circuit is operating in the first mode of operation or in the second mode of operation.
REFERENCES:
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patent: 5151994 (1992-09-01), Wille et al.
patent: 5557756 (1996-09-01), Spencer
patent: 5596729 (1997-01-01), Lester et al.
patent: 5652895 (1997-07-01), Poisner
patent: 6070205 (2000-05-01), Kato et al.
Jeddeloh Joseph
Larson Douglas A.
Rooney Jeffrey J.
Dharia Rupal
Park Vaughan & Fleming LLP
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