Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-28
2004-07-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06760892
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lithography process margin evaluating apparatus, and more specifically to a lithography process margin evaluating apparatus simulating a layout pattern of a semiconductor device in manufacturing a semiconductor.
2. Description of the Background Art
Lithography process is one of techniques to transfer a layout pattern of a semiconductor device to a semiconductor substrate. In a lithography process, a photosensitive resin (hereinafter, referred to as a photoresist) is first applied to the semiconductor substrate. Using an exposure apparatus, a layout pattern (hereinafter, referred to as a design layout pattern) on a mask is then exposed onto the photoresist on the semiconductor substrate. When the exposed photoresist is developed, the layout pattern of the transferred resin (hereinafter, referred to as an actual layout pattern) is formed. Through etching or ion implantation using the resin pattern, an actual layout pattern is formed on the semiconductor substrate.
In the lithography process, a transfer margin to the semiconductor substrate considerably varies, depending on optical conditions and shapes of design layout patterns. Accordingly, an actual layout pattern relative to a design layout pattern has conventionally been predicted with simulations.
FIG. 27
is a block diagram showing a configuration of a conventional lithography simulation apparatus.
Referring to
FIG. 27
, a lithography simulation apparatus
10
includes a hard disk
11
, a simulation unit
15
and an input unit
16
. Hard disk
11
includes a layout holding unit
12
, a simulation condition holding unit
13
and a simulation result holding unit
14
.
Layout holding unit
12
holds information of a design layout pattern input through input unit
16
. Simulation condition holding unit holds a simulation condition entered through input unit
16
. Examples of simulation conditions are exposure wavelength, Numerical Aperture (hereinafter, referred to as “NA”) and the like. Simulation result holding unit
14
holds a result from simulation performed at simulation unit
15
.
Simulation unit
15
simulates an actual layout pattern, using information of the design layout pattern held in layout holding unit
12
and the simulation condition held in simulation condition holding unit
13
. Information of the simulated actual layout pattern is held in simulation result holding unit
14
.
FIG. 28
is a flow chart showing an operation of the conventional lithography simulation apparatus.
Referring to
FIG. 28
, a user of lithography simulation apparatus
10
first enters information of the design layout pattern to lithography simulation apparatus
10
, using input unit
16
(step S
1
). Information of the entered design layout pattern is stored in layout holding unit
12
. The user then enters the simulation condition, using input unit
16
(step S
2
). The entered simulation condition is stored in simulation condition holding unit
13
. Simulation unit
15
within lithography simulation apparatus
10
simulates the actual layout pattern, using information of the design layout pattern and the simulation condition (step S
3
). The simulated actual layout pattern is stored in simulation result holding unit
14
(step S
4
). The user measures light intensity distribution within a photosensitive material and a shape of the actual layout pattern, using the simulation result stored in simulation result holding unit
14
(step S
5
). Thereafter, the user analyzes, for example, a difference in shape from the design layout pattern (step S
6
).
As described above, a conventional lithography process margin apparatus has performed a simulation of an actual layout pattern relative to a single design layout pattern.
In present days, since a design rule for a semiconductor device has been made smaller than a light source wavelength of an exposure apparatus, resolution of a layout pattern of the semiconductor device after transfer is lowered. In order to improve resolution, a special transfer technique called “resolution enhancement technique” is utilized.
In addition, in the actual layout pattern based on the design layout pattern, a distortion is caused through a manufacturing process. In order to correct the distortion caused therein, optical proximity correction (hereinafter, referred to as OPC) is widely used. Here, OPC is considered to correct process-originated distortions in general. Recently, OPC has become more complex because of smaller size of a semiconductor device. In addition to simply biasing a size of a design layout pattern as in a conventional example, some OPC creates a dummy pattern outside the design layout pattern. Accordingly, in order to determine a specification for OPC, an evaluation should be made for multiple design layout patterns.
As described above, as a semiconductor device is made smaller, a manufacturing process thereof has been changed. As a result, also in simulating a lithography process as well, a need has grown for analysis of a single design layout pattern as well as for margin evaluation of a lithography process with respect to a plurality of design layout patterns.
In a conventional lithography simulation apparatus, however, only a simulation of an actual layout pattern relative to a single design layout pattern was possible. Consequently, in order to perform lithography process margin evaluation for a plurality of design layout patterns, a user had to input a plurality of design layout patterns, enter a plurality of simulation conditions, and measure a plurality of actual layout patterns. Thus, operational burden to the user was significant.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a lithography process margin evaluating apparatus with high accuracy, capable of reducing operational burden.
A lithography process margin evaluating apparatus according to the present invention simulates, from a design layout pattern formed on a mask, a light intensity distribution within a photosensitive material on a semiconductor substrate and an actual layout pattern formed on the semiconductor substrate, and includes an analysis condition input unit, a layout pattern template holding unit, a simulation condition template unit, a measuring condition holding unit, a layout pattern generating unit, a simulation condition generating unit, a simulation unit, a measuring condition determining unit, and a measuring unit. The analysis condition input unit is for entering an analysis condition for analyzing the actual layout pattern. The layout pattern template holding unit stores a plurality of design layout pattern templates. The simulation condition template holding unit stores a plurality of simulation condition templates. The measuring condition holding unit stores a plurality of measuring conditions for measuring the actual layout pattern. The layout pattern generating unit selects a design layout pattern template, and generates a plurality of design layout patterns based on the analysis condition and the selected design layout pattern template. The simulation condition generating unit selects a simulation condition template, and generates a plurality of simulation conditions based on the entered analysis condition and the selected simulation condition template. The simulation unit simulates the actual layout pattern transferred to the photosensitive material on the semiconductor substrate, using the plurality of design layout patterns and the plurality of simulation conditions. The measuring condition determining unit determines a measuring condition among a plurality of measuring conditions based on the analysis condition. The measuring unit measures the actual layout pattern with the determined measuring condition.
Thus, the lithography process margin evaluating apparatus can generate a plurality of design layout patterns in accordance with the analysis condition, and simulate a plurality of actual layout patterns corresponding to the plurality of design layout patterns. In addition, the l
Nakae Akihiro
Taoka Hironobu
McDermott & Will & Emery
Renesas Technology Corp.
Siek Vuthe
Tat Binh C.
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