Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2001-11-13
2004-01-27
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
Reexamination Certificate
active
06683478
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a phase detector employed in a delay locked loop which delays an input reference clock signal by a predetermined time period. More specifically, the present invention is directed to a phase detector that maintains proper operation regardless of the point in time at which the operation of the delay locked loop is initiated.
BACKGROUND OF THE INVENTION
Delay locked loops (DLLs) are used extensively in the field of analog circuit design. With the increasingly stringent timing requirements of current high-performance computing and communication systems, DLLs are becoming more popular for use in digital circuit designs (e.g., computer motherboards, high performance multimedia boards, semiconductor memory devices, etc.). Particularly, DLLs are being used in semiconductor memory devices such as double data rate (DDR) DRAM to achieve a common phase between an input reference clock signal and an internal clock signal.
Referring to
FIG. 1
, a delay locked loop
1
includes a voltage controlled delay line (VCDL)
10
, a phase detector
20
, a charge pump
30
, a capacitor C
1
operating as a filter, and an optional delay unit
40
. The following description assumes the delay unit
40
is included in the delay locked loop.
The phase detector
20
measures the phase difference between an input reference clock signal REFCLK and an feedback clock signal FBCLK output from the delay unit
40
, and outputs phase difference detection signals UP and DOWN. The charge pump
30
controls an amount of output current Ic in response to the detection signals UP and DOWN. The capacitor C
1
provides the VCDL
10
with a control voltage Vc corresponding to the current Ic output from the charge pump
30
. The VCDL
10
delays the reference clock signal REFCLK by an amount of time corresponding to the control voltage Vc, and outputs a clock signal OUTCLK that is a delayed signal of the REFCLK. The delay unit
40
delays the clock signal OUTCLK output from the VCDL
10
by a predetermined time, and outputs a delayed signal of the OUTCLK so as to compensate for the phase difference between the OUTCLK and the REFCLK.
When a master reset signal RESETB is activated, the DLL
1
operates as follows. The RESETB signal has a high logic value when the DLL
1
is in operation. The phase detector
20
detects a phase difference between the input reference clock signal REFCLK and the feedback clock signal FBCLK output from the delay unit
40
. When the phase of the feedback clock signal FBCLK lags behind a phase of the reference clock signal REFCLK (or, the phase of REFCLK leads that of the FBCLK), the phase difference detection signal UP is enabled. Thus, the charge pump
30
provides output current Ic such that the delay time of the VCDL
10
is shortened. On the other hand, when the phase of the FBCLK leads the phase of the REFCLK (or, the phase of REFCLK lags behind that of the FBCLK), the phase difference detection signal DOWN is enabled. Thus, the charge pump
30
provides output current Ic so as to prolong the delay time of the VCDL
10
. As a result, the DLL
1
delays the reference clock signal REFCLK by the time period set in the VCDL to output an output clock signal OUTCLK.
Referring now to
FIG. 2
, the phase detector includes two D flip-flops
21
and
22
and a reset control circuit
23
.
The D flip-flop
21
includes an input terminal D coupled to a power supply voltage VCC, an output terminal Q outputting the phase difference detection signal UP, a clock terminal CK receiving the reference clock signal REFCLK, and a reset terminal RST.
The D flip-flop
22
includes an input terminal D coupled to the power supply voltage VCC, an output terminal Q outputting the phase difference detection signal DOWN, a clock terminal CK receiving a feedback clock signal FBCLK, and a reset terminal RST receiving a control signal A
0
output from the reset control circuit
23
.
The reset control circuit
23
is composed of a NAND gate
25
receiving the phase difference detection signals UP and DOWN to perform a NAND operation, and a NAND gate
24
receiving an output signal of the NAND gate
25
and an externally input master reset signal RESETB to perform an NAND operation.
The operation of the conventional phase detector will be described hereinafter with reference to the attached timing diagrams of
FIGS. 3A-B
and
FIGS. 4A-4D
. FIG.
3
A and
FIG. 3B
are timing charts illustrating the operation state of the phase detector
20
shown in
FIG. 2
while the DLL
1
of
FIG. 1
operates in a steady state. Specifically,
FIG. 3A
is a timing chart illustrating the states of phase difference detection signals UP and DOWN output from the phase detector
20
when the phase of the feedback clock signal FBCLK leads the phase of the reference clock signal REFCLK.
Referring now to FIG.
2
and
FIG. 3A
, when a phase of the feedback clock signal FBCLK leads a phase of the reference clock signal REFCLK with the master reset signal RESETB remaining high, the phase detection signal DOWN is synchronized with the FBCLK, so as to be enabled first. Thereafter, the phase detection signal UP is enabled in synchronization with the REFCLK. When both UP and DOWN signals are enabled, the NAND gate
25
in the reset control circuit
23
outputs a low level signal. Accordingly, the signal A
0
output from the NAND gate
24
goes high. Both D flip-flops
21
and
22
are then reset, allowing both of the UP and DOWN signals to transition to low. There is a simultaneous period of time when the detection signals UP and DOWN output from the phase detector
20
are both enabled. However, since the period of time that the DOWN signal is enabled is longer than the period of time that the UP signal is enabled, the charge pump
30
provides output current Ic such that the delay time of the VCDL
10
increases in proportion to the time difference between the UP and DOWN signals.
FIG. 3B
is a timing chart illustrating the states of phase difference detection signals UP and DOWN output from the phase detector
20
when the phase of the feedback clock signal FBCLK lags behind the phase of the reference clock signal REFCLK. Referring to FIG.
2
and
FIG. 3B
, when the phase of the FBCLK signal lags behind that of the REFCLK signal with the master reset signal RESETB at a high level, the phase detection signal UP is initially enabled in synchronization with the REFCLK signal. The phase detection signal DOWN is then enabled in synchronization with the FBCLK. When both the UP and DOWN signals are enabled, the NAND gate
25
in the reset control circuit
23
outputs a low level signal. Thus, the A
0
signal output from the NAND gate
24
transitions to high. As both of the D flip-flops
21
and
22
are reset in response to the high level of the A
0
signal, both the UP and DOWN signals transition to low. There is a period of time during which both the UP and DOWN signals output from the phase detector
20
are enabled. Nevertheless, since the enable period of the UP signal is longer than the enable period of the DOWN signal, the charge pump
30
provides output current Ic such that the delay time of the VCDL
10
is shortened in proportion to the time corresponding to the difference in time duration between the UP and DOWN signals.
Although not shown in the drawings, when there is no phase difference between the FBCLK and REFCLK, the enabled periods of the UP and DOWN signals are identical to each other. Accordingly, the delay time of the VCDL
10
is not adjusted.
The phase detector
20
outputs phase detection signals UP and DOWN for increasing, shortening or maintaining the delay time of the VCDL
10
. For this reason, the phase detector
20
is referred to as a three-state phase detector.
FIG.
4
A and
FIG. 4B
are timing charts illustrating operation states of the phase detector shown in
FIG. 2
when the DLL
1
of
FIG. 1
is changed, or initialized, from a non-operation state to an operation state. Specifically,
FIG. 4A
is a timing chart of signals output from the phase detector
20
in the
Mills & Onello LLP
Nu Ton My-Trang
Samsung Electronics Co,. Ltd.
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