Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2008-07-01
2008-07-01
Chase, Shelly (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
07395494
ABSTRACT:
An LDPC code encoding apparatus includes: a code matrix generator for generating and transmitting a parity-check matrix comprising a combination of square matrices having a unique value on each row and column thereof; an encoding means encoding block LDPC codes according to the parity-check matrix received from the code matrix generator; and a codeword selector for puncturing the encoded result of the encoding means to generate an LDPC codeword. The code matrix generator divides an information word to be encoded into block matrices having a predetermined length to generate a vector information word. The encoding means encodes the block LDPC codes using the parity-check matrix divided into the block matrices and a Tanner graph divided into smaller graphs in correspondence to the parity-check matrix.
REFERENCES:
patent: 6961888 (2005-11-01), Jin et al.
patent: 2003/0033575 (2003-02-01), Richardson et al.
patent: 2005/0246616 (2005-11-01), Choi et al.
patent: 1020020095749 (2002-12-01), None
patent: 1020030016720 (2003-03-01), None
Ahn Jae-Young
Kim Kwang-Soon
Kim Yun-Hee
Lee Sang-hyun
Blakely , Sokoloff, Taylor & Zafman LLP
Chase Shelly
Electronics and Telecommunications Research Institute
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