Electrical computers and digital processing systems: memory – Address formation – Operand address generation
Patent
1998-08-13
1999-09-28
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Operand address generation
711212, 711213, 711215, G06F 930
Patent
active
059604670
ABSTRACT:
An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.
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Mahalingaiah Rupaka
Tran Thang M.
Advanced Micro Devices , Inc.
Chan Eddie P.
Kivlin B. Noel
Merkel Lawrence J.
Nguyen T. V.
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