Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-05-19
2001-11-27
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000
Reexamination Certificate
active
06323673
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to buses and more particularly to termination of buses for use in information processing systems.
2. The Background Art
DESCRIPTION OF THE RELATED ART
In computer and information processing systems, various integrated circuit chips communicate digitally with each other over a common bus. The signal frequency at which this communication occurs can limit the performance of the overall system. Thus, the higher the communication frequency, the better. The maximum frequency at which a system communicates is a function not only of the time that it takes for the electromagnetic wavefronts to propagate on the bus from one chip to another, but also of the time required for the signals to settle to levels that can be recognized reliably at the receiving bus nodes as being high or low, referred to as the settling time.
The length of the settling time is a function of the amount of reflection and ringing that occurs on the transmission line. The more effective the termination of a bus system, the smaller the effects of reflection and ringing in the system and the shorter the overall settling time of the signal.
SUMMARY OF THE INVENTION
An information handling system includes a plurality of transmission lines coupled together at one end and having a characteristic impedance, a driver circuit coupled to one of the transmission lines, a plurality of receiver circuits individually coupled to distinct ones of the transmission lines for resolving the signals, and on-chip terminators having a output impedance corresponding to the characteristic impedance and that can be coupled or decoupled from a node by on-chip circuitry. In this embodiment, the terminators are separate and distinct from driver circuitry. However, when a node is in a receive configuration, its corresponding termination resistor is tied to the transmission line at that node, and its corresponding driver circuit presents a high impedance output to the node. A second embodiment provides driver circuits having particular on-chip pull-up and pull-down resistances, one of the either the pull-up or pull-down resistances being used to terminate the bus for those nodes which are in a receive configuration. In this second embodiment, separate terminators are not required, due to the driver operating as the terminator.
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Chang Daniel D.
Sierra Patent Group Ltd.
Sun Microsystems Inc.
Tokar Michael
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