Apparatus for determining the access time and/or the...

Details Apparatus for determining the access time and/or the... Apparatus for determining the access time and/or the...

2007-01-30

2007-01-30

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S815000, C711S167000

Reexamination Certificate

active

11036542

ABSTRACT:
An apparatus for determining the access time and the minimally allowable cycle time of a memory, comprising a clock for generating a signal which stimulates memory data output, programmable delay means for generating a delayed signal, sample-and-hold means for sampling the data output of the memory in response to the delayed signal, a comparator for comparing the sampled data to reference values, and a test status generator, wherein the test status depends on the results of more than one of the comparisons.

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patent: 6567941 (2003-05-01), Turnquist et al.
patent: 6570944 (2003-05-01), Best et al.

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