Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral monitoring
Reexamination Certificate
1994-06-30
2002-03-19
Follansbee, John A. (Department: 2154)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral monitoring
C711S005000
Reexamination Certificate
active
06360285
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to computer systems, and more particularly to the access of memory modules directly connected to a system bus of a computer system.
As it is known in the art, computer systems generally include at least one central processing unit (CPU) module, a main memory for storing data, at least one input/output (I/O) module, and a system bus coupling the aforementioned devices to the CPU module. The system bus typically includes data, address, and control lines.
Often, the main memory includes a plurality of memory modules each having an interface connected to the system bus. Each memory module contains semiconductor chips having a predetermined number of memory cells. The chips are often referred to as RAM, Random Access Memory, or DRAM, Dynamic Random Access Memory, in that each storage location is randomly addressable as distinguished from other types of memory devices such as magnetic tape or disk which are sequentially accessible, in that a number of storage locations are scanned before reaching the desired addressed location.
As an example, a 64 K memory chip has 2
16
or 65,536 addressable storage locations. Each storage location contains one memory cell which stores one binary bit of data.
The address range of the computer system is determined primarily by the number of address lines that are provided on the system bus. An address range of 0-64 K requires 2
16
permutations of 16 binary bits. Increasing the address bus by one line effectively doubles the previous address range of the system.
It should be noted that although memory capacity is related to the size of the address range, it is not the same as the address range. Most memory modules store multiple bytes of data at each addressable location. Thus, memory capacity is a function of the number of addressable locations (i.e., address range) and the amount of data stored at each location.
Generally each memory module responds to a different address range within the overall address range of the computer system. The size of each module's address range corresponds to the number of addressable locations on the module. The starting address of a module's address range may be determined by virtue of the position (i.e., backplane slot) in which the module is placed within the computer system, if each module has the same capacity, or the starting address may be assigned through the use of memory configuration software and hardware which determines the number of addressable locations of each memory module in the system prior to assigning address ranges.
CPUs, as well as other commander modules such as the I/O module, are capable of initiating transactions (i.e., read or write) to main memory on the system bus. In order to initiate a transaction on the system bus, a CPU must first gain control of the system bus which is often accomplished by arbitrating for the bus. Once the CPU has gained control of the system bus, the CPU drives an address and a command. If the command is a write to main memory, the CPU will also drive data.
The address driven indicates a location in main memory which the CPU wishes to read data from or write data to. Typically, when an address is driven, each memory module decodes the address to determine if the address being driven is within its address range such that it should respond.
There are often times when a memory module will be inaccessible because it is busy (i.e., unavailable) with another task, such as a memory refresh. Additionally, a memory module may be unavailable for a period of time following a write to main memory. Once the CPU transfers the data to the memory module, the transaction is complete and the system bus can be used by another module to initiate a transaction. However, the memory module generally requires additional time to complete the actual write of the data into the RAMs. Thus, if a subsequent read or write transaction is directed to the same memory module, the memory module may be unavailable and unable to respond.
A memory module may also be busy with another commander module's transaction in a computer system supporting a pipelined system bus. A pipelined system bus allows commander modules to initiate transactions with target modules, for example, memory modules, and then release the system bus such that it may be used by other modules. Subsequently, the target will gain control of the system bus and complete the earlier initiated transaction. In such a system, a first commander may initiate a transaction with a particular memory module and then release the system bus which is immediately controlled by a second commander. Where the second commander initiates a transaction with the same memory module, the memory module will be busy with the first commander's transaction, and thus, unavailable.
Many different techniques have been designed to handle unavailable memory modules, including having the CPU wait on the system bus until the memory module can respond or having the CPU release the system bus and retry the transaction at a later time. However, having the CPU wait on the system bus increases the time it takes to complete a transaction, prevents other commander modules from using the system bus for useful transactions (i.e., transactions which would complete). Furthermore, hardware must be designed to handle such unavailable conditions.
On the other hand, some techniques attempt to avoid a memory unavailable situation. For example, many computer systems partition the memory devices (i.e., RAM) of each memory module into multiple banks. The access circuitry of each bank responds to a different range of addresses allowing each bank to be independently accessed. Further, each bank has its own read and write circuitry such that each bank is entirely independent with the exception that each bank shares the memory module's system bus interface logic. The independent nature of the banks allows a write to a first bank to be followed immediately by a read or write to a second bank without having to wait for the write to the first bank to complete even when both banks are on the same memory module. Partitioning a memory module's addressable locations into independent banks increases the possibility that subsequent transactions will be to different banks, thus, reducing the number of times a CPU may have to wait or retry a memory access. However, an access by a first commander to a memory bank immediately followed by an access of the same memory bank by a second commander in a pipelined computer system will still result in a memory unavailable situation.
Another method which reduces the possibility of sending subsequent transactions to the same memory bank is to interleave memory. Interleaving is the practice of storing data in consecutive memory locations in alternating or successive memory banks. In a conventional 2-way interleaved memory, there is an “even” memory bank and an “odd” memory bank for each range of addresses. Any two sequential memory locations are stored in different memory banks. If two transactions access two sequential memory locations, the operation is as follows: the first location is written, for example, in a first memory bank and the second location is read, for example, from a second memory bank. Thus, since two sequential locations will be in different banks, they can be accessed very quickly without waiting for a write to complete. Other multiple way interleaving (i.e., 4-way, 8-way, etc.) may also be implemented.
The interleaved memory technique is based on the premise that there is a reasonably high probability that sequential accesses to memory will be in successive memory locations. Thus, sequential memory locations are placed in different banks so that they can be accessed quickly. The possibility remains, however, that sequentially issued transactions will be directed at the same memory bank with the result that a subsequent transaction will encounter an unavailable memory bank.
Another technique which avoids sending transactions to a memory bank which is unavai
Bloom Elbert
Fenwick David M.
Foley Denis
Hartwell David
Hetherington Ricky C.
Cesari & McKenna LLP
Follansbee John A.
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