Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Patent
1993-02-25
1995-03-21
Westin, Edward P.
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
341 96, 326 52, H03K 19094, H03K 1921
Patent
active
053999193
ABSTRACT:
Apparatus for generating an output signal in response to the change in state of any one of a plurality of input signals. The apparatus includes decoding means for each possible combination of input signals, and by an appropriate arrangement of these decoding means, ensures that any change in input signal status causes an output signal to be generated by the arrangement of decoding means. The decoding means includes first and second arrays 10,12, each comprising a matrix of MOS FET's; the FET's 30.sub.ij of the first array 10 are p-channel devices and the FET's 32.sub.ij of the second array 12 are n-channel devices. The matrix of each array is a paralleled configuration of series-connected branches of FET's functioning as decoders. The branches of each array decode input signal combinations of minimum distance two from one another. Arrays 10 and 12 are interconnected in such a manner that they draw no dc current (other than device leakage current). Any change in binary state of any one of the input signals results in the branches of FET's which decode the switch conditions alternating between n-channel and p-channel devices. As these alternations take place, the node 34 joining arrays 10 and 12 is switched between first and second voltage levels. A one shot circuit 14 converts each of these voltage transitions into an output signal pulse.
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Brady III W. James
Donaldson Richard L.
Maginniss Christopher L.
Roseen Richard
Texas Instruments Incorporated
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