Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
2002-07-09
2004-06-15
Nuton, My-Trang (Department: 2816)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C327S156000
Reexamination Certificate
active
06750725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for detecting a phase error of an input signal and a phase locked loop circuit using the same, and more particularly to an apparatus for detecting a phase error in accordance with a frequency and a phase change of a signal read from a disk-type storage medium, and a phase locked loop circuit using the same. The present application is based on Korean Application No. 2001-41016, filed Jul. 9, 2001, which is incorporated herein by reference.
2. Description of the Related Art
A system for recording and reproducing a signal to and from a disk-type storage medium such as a CD or a DVD records and reproduces the signal by rotating the disk-type storage medium at an equiangular velocity. In the system for recording and reproducing the signal by rotating at the equiangular velocity, when inside tracks, which are located at a center of a radius of the disk-type storage medium, are read, the linear velocity is slow. On the contrary, when outside tracks, which are located at an outer circumference of the radius, are read, the linear velocity is fast. Therefore, since a frequency between the inside tracks and the outside tracks of the disk-type storage medium varies over a large range, there is a need to use an algorithm, which is capable of improving a tracking function by detecting an exact timing error of a receiving signal, which is read from the disk-type storage medium, at a receiving end of the recording and reproducing system.
One example of the algorithm is the M&M (K. H. Mueller and M. Muller) method. The M&M method is disclosed in a thesis entitled “Timing recovery in digital synchronous data receiver” (IEEE Trans. Commun., vol. COM-14, pp.516-530, May 1976.)
FIG. 1
is a block diagram showing a structure of a conventional phase locked loop circuit according to the M&M method.
Referring to
FIG. 1
, the phase locked loop circuit is an apparatus for detecting a timing error and compensating for the timing error. The phase locked loop circuit
1
(hereinafter, referred to as a PLL) detects the timing error from the receiving signal, and synchronizes an input timing and a sampling timing of the receiving signal by compensating the timing error. The timing error in a time domain has the same meaning as a phase error in a frequency domain, thus the timing error and the phase error will be understood to have corresponding meanings hereinafter.
The PLL
1
comprises an A/D converter
10
, a phase error detect unit
14
, a low pass filter
16
, a D/A converter
17
, and a voltage controlled oscillator
18
(hereinafter, referred to as a VCO). The A/D converter
10
converts an analog signal into a digital signal. The phase error detect unit
14
detects the phase error from the digital signal input from the A/D converter
10
.
The low pass filter
16
removes high frequency noise included in the detected phase error. The D/A converter
17
converts the phase error passed through the low pass filter
16
into an analog signal. The VCO
18
compensates the sampling timing of the A/D converter
10
in accordance with the detected phase error. The PLL
1
includes an interpolation unit
5
for compensating an output characteristic of the PLL
1
to match a system incorporating the PLL
1
, for example an optical disk system.
A signal read from each track of the disk-type storage medium, such as a CD or a DVD, by an optical pickup that reproduces the signal from the disk-type storage medium is consecutively input to the A/D converter
10
of the PLL
1
. The A/D converter
10
converts the analog signal input from the optical pickup into a digital signal.
The phase error detect unit
14
consecutively receives the digital signal from the A/D converter
10
and obtains the timing error using a method which will be described later. The timing error obtained by the phase error detect unit
14
is input to the low pass filter
16
. The low pass filter
16
removes the high frequency noise from the received timing error and inputs the filtered response to the D/A converter
17
.
The D/A converter
17
converts the phase error signal, from which the noise has been removed, into an analog signal. The VCO
18
shifts the phase in accordance with the phase error signal to compensate the timing error of the received signal. A/D converter
10
converts the received analog signal into the digital signal at the sampling timing that has been compensated by the shifted phase. The interpolation unit
5
receives the digital signal converted in accordance with the compensated sampling timing, and outputs a controlled signal to match the optical disk system.
According to the described M&M algorithm, the timing error is detected by a mathematical expression 1.
Z
k
=0.5(
X
k
a
k−1
−X
k−1
a
k
) [Mathematical expression 1]
FIG. 2
is a block diagram showing the result of the above expression. Referring to
FIG. 2
, the phase error detect unit
14
comprises a quantization unit
142
, a pair of buffers
141
and
143
, two multipliers
144
and
145
, a subtractor
146
, and an amplifier
147
.
The buffer
141
receives the digital signal from the A/D converter
10
and stores the digital signal. After the digital signal x
k−1
is input, if a new digital signal x
k
is input, the digital signal x
k−1
is stored in the buffer
141
.
The quantization unit
142
receives a new digital signal x
k
from the A/D converter
10
, and outputs a value a
k
, which has been 2-value quantized as +1 or −1 in accordance with the digital signal value, to buffer
143
. At this time, an output value a
k−1
of the quantization unit
142
by the digital signal x
k−1
is stored in the buffer
143
. The multiplier
144
receives the output value x
k−1
of the buffer
141
and the output value a
k
of the quantization unit
142
based on the new digital signal x
k
.
The multiplier
145
receives the output value x
k
of the A/D converter
10
and the output value a
k−1
of the buffer
143
. The subtractor
146
obtains the timing error by receiving the value of the multipliers
144
and
145
. The amplifier
147
amplifies the obtained timing value by a factor of a half.
FIG. 3
is a graph showing a characteristic of the phase error detect unit
14
of FIG.
2
. Referring to
FIG. 3
, a dotted line “A” illustrates an ideal distribution of a timing function value. The straighter the line, the greater is the probability for the timing function value to detect the timing error.
However, a conventional timing function value is shown as an s-type solid line “R”. In other words, the conventional timing function value does not satisfy the linear characteristic. The conventional apparatus for detecting a timing error detects the timing error for every sampling clock.
Moreover, as shown in
FIG. 8
, when the conventional apparatus for detecting a timing error is used, noise generates a large dispersion value in a steady status, when tracking the phase error. In other words, if there is much noise, the error generating probability around the real error value is also high.
In addition, as shown in
FIG. 9
, when the conventional apparatus for detecting a timing error is used, a normal jitter value is large when tracking the timing error. Therefore, the function of the conventional apparatus for detecting a timing error cannot be assured when a multi-level signal is transmitted in the baseband. Also, when the signal to noise ratio is low, the function cannot be assured.
Moreover, the CD and the DVD system use a run-length limited code signal that is a zero crossing shift of the signal. The signal is irregular and is multi-level. However, when the conventional apparatus for detecting timing error is used, the timing error value is shown in every sampling clock. Thus, there is a problem that the dispersion values of the data sample values show a considerably great variation value in accordance with the influence of the SNR (signal to noise ratio), as shown in
Choi Hyung-Jin
Kim Pan-Soo
Ko Seok-Jun
Lee Jae-Wook
Nuton My-Trang
Samsung Electronics Co,. Ltd.
Sughrue & Mion, PLLC
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