Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2000-06-27
2003-12-23
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S502000, C327S020000
Reexamination Certificate
active
06668334
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the field of integrated circuits. More particularly, the invention pertains to an apparatus for detecting a clock failure in an integrated circuit.
BACKGROUND OF THE INVENTION
Digital and mixed-signal integrated circuits (ICs) usually depend on the presence of a clock, a signal consisting of a repetitive and ideally unchanging sequence of alternating digital ‘1’s and ‘0’s, to drive the sequential digital logic within these circuits. If the clock signal is disrupted, or stopped altogether, the digital circuits triggered off of this clock may function incorrectly or cease operation altogether. Such a disruption or stopping of the clock is referred to in the art as a “loss of clock.” A loss-of-clock (LOC) detector—a circuit that monitors the clock signal and asserts a warning signal (flag) when the clock is disrupted—is thus clearly important in critical systems. The loss-of-clock detector warning signal may be used to indicate to the system controller that the clock has been disrupted, and that the data processed by the digital subsystems that depend on this clock may be corrupted. Alternatively, the warning signal may be used to force automatic selection of an alternative clock source if the primary clock signal is disrupted.
The concept of a loss-of-clock detector is well known in the art. As indicated in
FIG. 1
, a typical LOC detector
100
is implemented by using pull-up resistor
101
to charge capacitor
102
up to the supply voltage
103
, and by using grounded switch
104
to discharge capacitor
102
. A clock edge detector
105
causes switch
104
to close momentarily after each rising edge (transition from logic ‘0’ to logic ‘1’) and after each falling edge (transition from logic ‘1’ to logic ‘0’) of the input clock, CLK. The voltage across capacitor
102
is input to comparator
106
, the output of which is the loss-of-clock signal (LOCFLG)
107
. Comparator
106
operates in such a way that LOCFLG
107
is logic ‘1’ whenever the comparator input voltage exceeds the comparator trip voltage and logic ‘0’ otherwise. The comparator trip voltage is equal to the voltage of Voltage Reference
108
, V
TR
.
The values of resistor
101
and capacitor
102
are chosen so that the resulting resistor-capacitor (RC) time constant, R
PU
×C, is much higher than the expected time between transitions or edges of CLK. Thus, if the input clock is operating normally, switch
104
is closed often enough to prevent resistor
101
from charging capacitor
102
past the comparator trip voltage. However, when the clock stops functioning, switch
104
remains open and capacitor
102
is charged up towards V
DD
. Once the voltage across capacitor
102
passes the trip voltage, V
TR
, of comparator
106
, loss-of-clock signal
107
goes to logic ‘1’, indicating that the input clock has stopped.
Referring to
FIGS. 2A-C
, in a typical timing diagram of the LOC detector function, the input clock signal CLK is monitored for rising and falling edges whose presence holds the voltage across the capacitor
102
low, and thus the loss-of-clock signal (LOCFLG) is held low as shown. Following the final transition of the disrupted input clock, after the detection time, T
LOC
, the output of the loss-of-clock detector
100
, LOCFLG, is asserted high.
In an ideal case, the value of T
LOC
would be a specific number of clock periods (cycles). However, due to the impreciseness of manufacturing tolerances of integrated circuits, the value of T
LOC
varies greatly. Referring to
FIG. 2C
, the desired detection time window is typically set by system level concerns such as detecting the disruption of a clock within a certain time interval of the disruption occurring. The desired detection time window opens (begins) a small time interval, T
DECMIN
, after the final transition of the disrupted input clock. The desired detection time window closes (ends) after a larger time interval, T
DECMAX
, following the final transition of the disrupted input clock. Manifestly, T
DECMAX
is greater than T
DECMIN
, and T
DECMIN
may be zero, which means the desired detection window opens coincident with the final transition of the input clock. An operational (functional) loss-of-clock detector
100
asserts LOCFLG so that T
LOC
is greater than T
DECMIN
and less than T
DECMAX
. When the input clock signal is restored, transitions or edges resume. As shown, coincident with the first transition of the restored input clock, the loss-of-clock signal is de-asserted low.
A drawback to this prior art LOC detector is that the detection time, T
LOC
, is set by the R
PU
×C time constant. Accordingly, manufacturing variations in R
PU
or C, which can be for example as large as 50% of the nominal component values, or variation of R
PU
with chip temperature, which can be for example as large as 20% over the specified operating temperature range of most integrated circuits, limit how precisely T
DECMIN
and T
DECMAX
can be controlled, thus leading to a large detection time window. In addition, since R
PU
and C are fixed quantities, the time constant R
PU
×C does not vary with the frequency of the input clock, F
CLK
. Thus when F
CLK
>>1/(R
PU
×C), a significant number of clock periods pass before the circuit detects that the clock has been lost.
Alternative LOC detector architectures that partially overcome these drawbacks are also known from the prior art; however, each of these architectures introduces a new set of drawbacks. For example, pull-up resistor
101
in
FIG. 1
can be replaced by a constant current source; the resulting time constant that controls T
LOC
is insensitive to resistor variation. However, this circuit requires a well-controlled current source, which may require a manual tuning process; further, this improvement fails to mitigate the effect of capacitor variation, or the variation of frequency of the input clock.
An LOC detector can also be implemented without any precision analog components by using a secondary clock and digital circuitry to sample the primary input clock, keeping track of how much time has elapsed since the previous transition. Obviously, this requires a second clock, something that may not be available in every system. Further, if the secondary clock itself fails, the detector that monitors the primary clock will also fail.
SUMMARY OF THE INVENTION
Briefly stated, an apparatus for detecting a failure of an input clock and generating a loss-of-clock signal includes a frequency-to-current converter for generating a charging current substantially proportional to a frequency of the input clock, capacitor for accepting the charging current and providing a terminal voltage that changes in response to the charging current, an edge detector receiving the input clock signal as an input and producing an output pulse on an edge of the input clock signal, a first switch coupled to the capacitor such that the capacitor is discharged to a reference potential when the first switch is closed, and wherein the first switch is controlled by the edge detector to close when the edge detector output pulse is asserted, and comparator for generating a loss-of-clock signal when the voltage on the capacitor passes (i.e., exceeds or drops below) a specified value of trip voltage.
The frequency-to-current converter of the loss-of-clock detector of the present invention avoids the disadvantages of prior art circuits by providing a value of output current substantially linearly proportional to the frequency of the input clock and to a second capacitor whose capacitance tracks the capacitance of the first capacitor. As a result, T
LOC
is substantially equal to a fixed number of clock periods and virtually independent of varying clock frequency, manufacturing process variations, and chip temperature, allowing for a significant narrowing of the desired detection time window over current state of the art circuits.
REFERENCES:
patent: 4142159 (1979-02-01), Ingram et al.
patent: 4144448 (1979-03-01), Pisciotta et al.
patent: 4374361 (1983-02-01),
Abel Christopher John
Mastrocola Angelo Rocco
Sherry Douglas Edward
Wilson William Burdett
Du Thuan
Heckler Thomas M.
Lucent Technologies - Inc.
LandOfFree
Apparatus for detecting clock failure within a fixed number... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for detecting clock failure within a fixed number..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for detecting clock failure within a fixed number... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3174409