Apparatus for delivering precise traps and interrupts in an out-

Electrical computers and digital processing systems: processing – Processing control – Branching

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712218, 712200, G06F 930

Patent

active

060498684

ABSTRACT:
In a processor executing instructions speculatively or out-of-order, an apparatus for tracking traps, exceptions, and interrupts within the processor. A table stores front-end and back-end traps associated with an instruction, and an instruction retirement module retires the instructions in order if no traps were associated with older instructions in the processor. In this way, the proper trap sequence of events is maintained so that traps can be properly handled.

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