Television – Bandwidth reduction system – Data rate reduction
Patent
1998-04-10
1999-10-26
Tung, Bryan
Television
Bandwidth reduction system
Data rate reduction
348423, 348845, 3488451, H04N 712, H04N 724, H04N 730
Patent
active
059737441
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for decoding video data, and more particularly, to an apparatus for decoding video data on a real-time basis by restoring DC coefficients of intra-macroblocks via a decoding path different from those for decoding other coefficients.
DESCRIPTION OF THE RELATED ART
Generally, a decoder relating to an MPEG (Moving Pictures Experts Group) standard receives a bitstream which is coded by an encoder and transmitted, and restores the received bitstream to the original data before encoding on the basis of the analysis of header information contained in the received bitstream. A general video decoder can decode data of a main level having a small amount of encoding at the operating speed of a system clock. Therefore, header information and encoded data can be processed via a single path.
However, a video decoder, such as for high-definition TV (HDTV) which processes a bitstream belonging to a main profile and high level in the MPEG standard, requires a system clock of at least 100 MHz in order to perform high-speed data processing since there is a large amount of data to be processed. It is difficult to implement such a system in hardware, and the manufacturing cost of such an implementation is excessively high.
A technique for reducing the burden of a system clock in a system for decoding video data in an HDTV is disclosed in Korean Patent Application No. 95-43583, which is by the applicant of the present invention. This prior art discloses a decoding apparatus for decoding via two paths four luminance blocks and two chrominance blocks which constitute a macroblock relating to a 4:2:0 picture format. This decoding apparatus can process a video bitstream at a high speed without increasing the speed of system clock.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an apparatus for decoding video data in which, among data output from a variable length decoder, data involving DC coefficients of an intra-macroblock is decoded via a decoding path different from those of other coefficients. Accordingly, the apparatus according to the invention can restore the DC coefficients on a real-time basis, while reducing its decoding burden.
To accomplish the above object of the present invention, there is provided a decoding apparatus for decoding symbols and header data obtained by variable length decoding, the decoding apparatus comprising:
a data distributor for receiving the symbols and alternately outputting blocks of the symbols via two output terminals;
a header analyzer for receiving the header data, analyzing the received header data and outputting parameters relating to restoration of the symbols;
DC component decoding means for detecting symbols relating to DC coefficients of an intra-macroblock among the symbols output from the data distributor, and restoring the DC coefficients of the intra-macroblock, using the detected symbols and the parameters supplied from the header analyzer; and
first and second restoring units which are individually connected to two output terminals of the data distributor, for restoring the symbols input from the data distributor in units of a block, using the parameters generated by the header analyzer and a corresponding DC coefficient of the DC coefficients produced by said DC component decoding means.
BRIEF DESCRIPTION OF THE DRAWINGS
The preferred embodiment is described with reference to the drawings wherein:
FIG. 1 is a block diagram of a decoding apparatus according to a preferred embodiment of the present invention;
FIGS. 2A to 2L are timing diagrams for explaining the operation of the decoding apparatus of FIG. 1;
FIGS. 3A to 3L are timing diagrams for explaining the operation of a DC decoding unit;
FIG. 4 is a conceptual diagram for explaining reset points in time of DC predictors within a macroblock; and
FIGS. 5A to 5E are timing diagrams for explaining the latching operation of decoded DC coefficients.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1 illu
REFERENCES:
patent: 5107345 (1992-04-01), Lee
patent: 5557538 (1996-09-01), Retter et al.
patent: 5686915 (1997-11-01), Nelson et al.
patent: 5825934 (1998-10-01), Ohsawa
patent: 5828425 (1998-10-01), Kim
Samsung Electronics Co,. Ltd.
Tung Bryan
Vo Tung
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