Apparatus for correcting data of layout pattern

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06848096

ABSTRACT:
An apparatus for correcting layout pattern data composed of a computer system includes eight sections. The first section holds the layout pattern data. The second section holds correcting requirements. The third section extracts and divides correction target edges of the layout pattern. The fourth section sets a permissible correction range. The fifth section extracts insufficient process margin parts. The sixth section resets the permissible correction range. The seventh section performs correction by simulation. The eighth section holds finished correction layout pattern data. By simulation, the apparatus predicts finished layout patterns at high rate and high precision within the movable range of the correction target edges which can secure process margins.

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patent: 20030097647 (2003-05-01), Pierrat et al.
patent: 20030115569 (2003-06-01), Ikeuchi
patent: 2001-100390 (2001-04-01), None
patent: 2001-188336 (2001-07-01), None
Calibre WORKbench and LITHO Commands Reference Manualv.8.8_11 (Jun. 2001) pp. 3:51-3:52.
“Customizing Proximity Correction for Process-Specific Objectives” Michael L. Rieger, et al.SPIEvol. 2726 (1996).

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