Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
1999-01-06
2001-04-17
Chaudhuri, D. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S707000, C257S710000, C257S713000, C257S778000, C361S709000
Reexamination Certificate
active
06218730
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is generally directed to structures and methods for controlling the thickness of the gap between an electronic circuit chip and a lid, heat sink or other cooling mechanism. More particularly, the present invention is directed to a system in which the size of the gap between the circuit chip and the lid or heat sink is controlled and even more particularly controlled so that this gap is made to be as small as possible without deleteriously effecting the assembly process or chip integrity. Even more particularly, the present invention is directed to a system for controlling the thickness of thermal paste material disposed between either a single chip or multi-chip module and its lid or cover.
As device integration levels keep on increasing, the demand for a more efficient solution to the cooling of high power electronic circuit chips becomes an even more important ingredient in achieving required system performance. The use of thermal paste or gel to cool single chip or multi-chip modules is highly desirable because of its simplicity and high thermal performance. Thermal pastes are also not impacted by small particle contamination; hence, module assembly can be done in non-clean room environments, which is a factor in helping to reduce module assembly costs. Furthermore, the compliance of thermal pastes allows them to absorb mechanical tolerances that are associated with chip height and hardware variations.
An additional method for providing efficient cooling for electronic circuit chips is the use of solder between the chip and its corresponding module lid. In such cases, the chip backside is metallized and solder is wetted to both lid and chip surfaces such that when the solder is reflowed, a joint is achieved between the chip and the lid. Solder has a thermal conductivity about ten times the thermal conductivity of the best thermal paste available; hence it provides a significant improvement in thermal performance over thermal pastes. However, the compliance advantages of thermal pastes can be achieved while simultaneously improving thermal conductive characteristics through control of paste thickness in the gap between chip and lid.
It is known that it is desirable for electronic devices to operate at low temperatures for enhanced performance and reliability. This is particularly true for CMOS devices where a 10° C. reduction in temperature produces approximately a 2% gain in system speed.
To a first order of approximation, the temperature of the chip is given by the following one-dimensional equation:
T
chip
=T
air
+P
chip
×R
int
+P
mod
×R
ext
In the case of a single chip module, the module power equals the chip power, and the above equation simplifies to:
T
chip
=T
air
+P
chip
×(
R
in
+R
ext
)
In the above equations, R
in
represents the internal thermal resistance of the module, that is the resistance from the chip up through the thermal paste to the module lid, whereas R
ext
represents the thermal resistance external to the module, that is the lid-to-heat sink interface plus the heat sink resistance, including air heating effects.
The internal thermal resistance is composed of three resistances in series:
R
in
=R
chip
+R
paste
+R
lid
Since the lid is typically made of a high thermal conductivity material such as aluminum, the thermal paste resistance is the largest contributor to the internal thermal resistance, R
in
. Reduction of the thermal paste resistance is therefore a significant factor in reducing the overall device temperature.
The thermal resistance of paste is given by the following equation:
R
paste
=L
gap
/(
K
paste
×A
chip
)
where L
gap
is thickness of the paste between the chip and module lid, K
paste
is the paste thermal conductivity, and A
chip
is the area of the chip. It is clear from this expression that reduction of the paste thermal resistances, R
paste
, can only be accomplished via either (i) reduction of the paste gap size and/or (ii) an increase in the thermal conductivity of the thermal paste.
Current designs use the compliance of the thermal paste to accommodate variations in the thermal paste gap. The tolerances are mainly driven by the tolerances on the chip thickness, tolerances for the chip solder balls and by tolerances on the hardware ans substrate. The statistical variations of these tolerances are typically between ±0.003 to 0.004 inches. Since the thermal paste “squeeze force” goes up exponentially as the paste is squeezed into very small gaps, that is into gaps under 0.003 inches, any single chip or multi-chip module should be designed to achieve a thermal paste gap of at least 0.007 inches under normal conditions. The statistical maximum paste gap therefore becomes 0.010 to 0.011 inches.
If solder is used between the chip and the module lid, it is still necessary to consider the same type of design tolerances as with thermal paste alone. While paste gap control for solder is not as critical to thermal performance, the apparatus and method disclosed herein for controlling the thermal paste gap is also employable to achieve optimum solder fillet shape since this can have an impact on solder reliability during thermal cycling. Accordingly, via the present invention, thermal paste cooling becomes more efficient and the solder thermal interface becomes more reliable. (It is noted that it is the higher thermal conductivity of solder which tends to reduce design tolerance problems as compared with the use of thermal paste alone).
The present invention provides a structure and a method for controlling the gap between the chip and a module lid while still maintaining the chip and its interconnect structure within a sealed environment. The sealed package is desirable to prevent moisture from contacting the chip, particularly over long periods of time. Accordingly, the improved use of thermal paste cooling, as employed in the present invention becomes more efficient and even solder based cooling systems become even that much more reliable.
SUMMARY OF THE INVENTION
In a preferred embodiment of the present invention an electronic chip assembly is provided for controlling thermal paste thickness. In particular, a substrate having electrical conductors is provided together with an electronic circuit chip which is affixed face down to the substrate so as to make electrical contact between the circuit chip and electrical conductors on the substrate. A thermal paste is disposed on the non-face down side of the circuit chip. A substantially flat thermally conductive lid is disposed over the chip and in thermal contact with the paste. In one embodiment the lid possesses a greater horizontal extent than the chip and therefore has a lid portion which overhangs the chip. Furthermore from this overhanging lid portion there depends a male lid sealing ring around the periphery of the lid. Additionally there is provided a corresponding female channel on the substrate. This channel has sidewalls and there is sealant disposed within the channel so as to form a seal between the sidewalls of the channel and the downwardly depending male lid sealing ring.
In another embodiment of the present invention instead of employing a female channel on the substrate, a female channel is disposed in the thermally conductive lid and a corresponding male ceiling ring is disposed on the substrate. This male sealing ring possesses a T-shaped cross section with the vertical portion of the “T” extending into sealant which is disposed between the sealing ring and the sidewalls of the female channel receptacle in the lid portion.
In yet another embodiment of the present invention which also employs a female receiving channel in the lid, a T-shaped male sealing ring is employed. However, in this embodiment the male sealing ring having a T-shaped cross section is disposed along the outer periphery of the substrate with the normally vertical portion of the “T” being disposed in a horizontal position sealed to the substrate. The normally horizonta
Sherif Raed A.
Toy Hilton T.
Anderson Jay H.
Chambliss Alonzo
Chaudhuri D.
Cutter Lawrence D.
International Business Machines - Corporation
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