Apparatus for controlling test mode of semiconductor memory

Details Apparatus for controlling test mode of semiconductor memory Apparatus for controlling test mode of semiconductor memory

2006-12-22

2010-12-28

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S230030, C365S189020

Reexamination Certificate

active

07859924

ABSTRACT:
Disclosed is a test mode control apparatus of a semiconductor memory having a plurality of banks divided into first and second bank groups, a plurality of pads, and a test mode controller. The test mode controller outputs data to the pads from one of the first and second bank groups and then outputs data to the pads from the other of the first and second bank groups.

REFERENCES:
patent: 5511029 (1996-04-01), Sawada et al.
patent: 5959911 (1999-09-01), Krause et al.
patent: 5959930 (1999-09-01), Sakurai
patent: 6076136 (2000-06-01), Burroughs et al.
patent: 6094337 (2000-07-01), Ueda et al.
patent: 6175528 (2001-01-01), Kye
patent: 6430101 (2002-08-01), Toda
patent: 7002364 (2006-02-01), Kang et al.
patent: 2002/0051401 (2002-05-01), Lee
patent: 2005/0195666 (2005-09-01), Hong et al.
patent: 2007/0014168 (2007-01-01), Rajan
patent: 2004178672 (2004-06-01), None
patent: 1019990077482 (1999-10-01), None
patent: 1020050094113 (2005-09-01), None

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