Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-11-19
2001-10-02
Thai, Tuan V. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S005000, C711S168000
Reexamination Certificate
active
06298413
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to circuitry and protocols associated with operating a memory device, and more particularly, to apparatus for controlling refresh operations in a dynamic random access memory device.
BACKGROUND OF THE INVENTION
FIG. 1
is a simplified functional block diagram of a memory device
200
that represents any of a wide variety of currently available memory devices. The central memory storage unit is a memory array
202
that is arranged in a plurality of banks, with two such banks
204
A and
204
B shown. The memory array
202
includes a plurality of individual memory elements (not shown) for storing data, with the memory elements commonly arranged in separately addressable rows and columns, as is well known.
Particular locations within the memory array
202
are addressable by Address signals that external circuitry such as a memory controller (not shown) provides to the memory device
200
. The memory controller also provides a plurality of Control or command signals that are used to designate the particular memory access type and/or sequence of memory accesses. As depicted in
FIG. 1
, a control/address logic circuit
206
receives the Control and Address signals, which may be provided in parallel signal paths, serially, or some suitable combination. The control/address logic circuit
206
then applies a plurality of internal control signals to control the timing and sequence of operations accessing the banks
204
A and
204
B via access circuits
208
A and
208
B, respectively. Those skilled in the art will understand that the depicted access circuits
208
A and
208
B represent a collection of various functional circuit components commonly found in memory devices. Examples include row and column address latch, buffer, and decoder circuits, sense amplifiers and I/O gating circuitry, and other well-known circuits adapted for particular memory device implementations.
Data written to and read from the memory array
202
is transferred from and to the memory controller or other external circuitry via a data I/O circuit
210
and the access circuits
208
A and
208
B. Those skilled in the art will also understand that the depicted data I/O circuit
210
represents a collection of various functional circuit components adapted to transmit data to or receive data from external circuitry and to correspondingly receive read data from or transmit write data to the array
202
via the access circuits
208
A and
208
B.
As known to those skilled in the art, data stored in dynamic random access memories (DRAMs) deteriorates with time and must be periodically “refreshed” to maintain accurate data. The control/address logic circuit
206
then includes a refresh control/address circuit
212
that provides the necessary control signals and address information to refresh the data contents of the array
202
. Operation of the refresh control/address circuit
212
is commonly initiated in response to a command from the memory controller, such as the well known Auto Refresh command.
The memory device
200
depicted in
FIG. 1
exemplifies multibank DRAMs, such as synchronous DRAMs (SDRAMs) and packet-oriented DRAMs (known as SLDRAMs). SDRAMs, commonly have two array banks, and SLDRAMs commonly have eight array banks. Providing multiple banks improves the average speed with which a sequence of memory operations can be performed. When access to a particular array bank is complete, a “precharge” operation is performed to prepare the corresponding access circuitry for a subsequent data transfer operation with the array bank. The precharge operation requires a certain amount of time for its completion, and therefore limits the speed with which a sequence of memory operations can be performed to a particular array bank. By organizing the memory array to have multiple banks with associated access circuits, the precharge time can, in some instances, be “hidden.” For example, if a first access is to bank
204
A and a subsequent access is to bank
204
B, precharge operations associated with bank
204
A can occur while initiating memory access operations to bank
204
B.
Initiation of Auto Refresh operations cannot occur, however, until the memory device
200
is idle—namely, no memory operations are occurring and all array banks and associated access circuits have been precharged. Thus, while providing a multiple bank configuration can improve data transfer speeds for some sequences of memory operations, refresh operations still adversely effect data transfer rates.
Referring to
FIG. 2
, a timing diagram depicts the operation of an SLDRAM in accordance with the prior art. As is known to those skilled in the art, control and address information is provided to the SLDRAM as a sequence of packets, each of which is registered at a clock “tick” (a rising or falling edge of a command clock signal). The timing diagram depicts commands provided as a sequence of four packets of control/address information CA
0
-CA
9
. The commands are registered at times referenced to the command clock signal CCLK, and the data input to or output from the SLDRAM is a sequence of four packets of data DQ
0
-DQl
7
.
Referring to
FIG. 2
, a first command is registered during a 10 nanosecond time interval. The first registered command is a bank read and close command addressed to a location in a bank
0
. Following the bank read time interval tBR (also known as read latency), data read from bank
0
is then delivered as a sequence of four data packets. The well-known open-to-close row command period tRAS and precharge time period tRP are also shown. Because all access to the SLDRAM must cease prior to conventional refresh operations, the four packet Auto Refresh command registration is limited by the open-to-close row and precharge time intervals, as shown. Following registration of the Auto Refresh command, further command registration is limited by the refresh command period tRC. Only then can a subsequent access be initiated, such as the depicted read and close operation to a location in a bank
2
. As shown in
FIG. 2
, conventional refresh operations in an SLDRAM result in a significant time lapse between registration of successive read commands. Multibank DRAM refresh operations in accordance with the prior art significantly and adversely affect the speed at which consecutive data transfer operations can be performed.
SUMMARY OF THE INVENTION
In accordance with the invention, a memory controller is provided for controlling operations of a multibank memory. The memory controller includes a request buffer, a refresh requester, and a control state machine. The request buffer stores a pending data transfer request, and the refresh requester produces a refresh request. The control state machine is coupled with the request buffer, and responds to receiving the data transfer request by applying a first set of control signals to the memory to initiate data transfer operations. The control state machine is also coupled with the refresh requester, and responds to receiving the refresh request by applying a second set of control signals to the memory to initiate refresh operations. The control state machine initiates refresh operations addressed to a first of the banks while data transfer operations are being executed in a second of the banks. The memory controller may also include a request arbiter coupling the control state machine with the request buffer and with the refresh requester, with the request arbiter selectively transmitting either the data transfer request or the refresh request to the control state machine.
In one aspect of the invention, a memory controller is provided for controlling operations of a multibank memory that registers commands and requires a minimum command time interval between successive registration of commands addressed to the same bank. The memory controller includes request buffer circuitry, refresh request circuitry, and control state circuitry. The data transfer request circuitry stores at least one data transfer request and provides this request to the
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Thai Tuan V.
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