Apparatus for capturing data on a debug bus

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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Reexamination Certificate

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07107394

ABSTRACT:
In one embodiment, an apparatus is disclosed for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; and logic for comparing a value of the counter with a preselected register address on each count of the counter, wherein the logic for comparing comprises a comparator having an input connected to receive the preselected register address, an input connected to receive the value of the counter, and an output operable to drive a select signal of a multiplexer provided for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address.

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patent: 6158023 (2000-12-01), Ubukata et al.
patent: 6625684 (2003-09-01), Casey et al.
patent: 6772269 (2004-08-01), Kaganoi
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Examination Report Under Section 18(3) dated Jul. 28, 2005; 2 pages.
Search Report under Section 17 in GB0405431.8 from the UK Patent Office (date of search Jul. 15, 2004), 1 page.
Bart Vermeulen and Sandeep Kumar Goel, “Design for Debug: Catching Design Errors in Digital Chips”, IEEE Design & Test of Computers; May-Jun. 2002; pp. 37-45.

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