Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-01-30
2007-01-30
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C365S189050
Reexamination Certificate
active
10999500
ABSTRACT:
Disclosed is a device for calibrating termination voltage of an on-die termination. The device for calibrating termination voltage of an on-die termination for a semiconductor memory device having a DLL device, comprises an on-die termination enable signal generating part for outputting an ODT enable signal for driving the on-die termination (ODT) when a signal DLL Reset EMRS is applied, a counter circuit of for outputting a plurality of counter signals, an on-die termination (ODT) including a variable resistor part controlled by the counter signals outputted from the counter circuit and outputting a variable termination voltage according to a resistance value of the variable resistor part, and a first control part for comparing a reference voltage with the termination voltage and outputting a control signal for controlling the counter circuit according to a comparison result.
REFERENCES:
patent: 5666078 (1997-09-01), Lamphier et al.
patent: 6307791 (2001-10-01), Otsuka et al.
Chang Daniel D.
Hynix / Semiconductor Inc.
Ladas & Parry LLP
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