Computer graphics processing and selective visual display system – Computer graphics display memory system – Logical operations
Reexamination Certificate
1995-06-07
2002-08-20
Zimmerman, Mark (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Logical operations
C345S561000, C345S563000, C345S564000
Reexamination Certificate
active
06437790
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a digital processing system and, particularly, to a method and apparatus for bit operational process suitably used in an image processing system having a bit-map display.
Which result when this image processing is implemented on a conventional system, with reference to FIG.
3
. Referring to
FIG. 1
reference symbol M
1
denotes a memory area storing image data in 1-to-1 correspondence to a CRT (Cathode Ray Tube) screen, M
2
denotes a memory area storing image data to be added to the image data in M
1
, X
A
and X
B
denote partial areas in M
1
and M
2
, respectively, for which image data processing takes place, W
A0
, W
A1
, WA
A2
, WB
B0
and W
B1
denote boundaries of data words having a word length of 16 bits, for example, R
0
through R
m
represent raster lines for the partial areas X
A
and X
B
, na and nb represent dis-placements of the leading edges of the areas X
A
and X
B
from the word boundaries W
A0
and W
B0
, respectively, A
0
through A
n
and B
0
through B
n
represent addresses of word data in the areas X
A
and X
B
, and MFY denotes a modification unit for implementing the alignment and processing for the areas X
A
and X
B
having different starting bit positions na and nb.
Since the currently available processing unit such as a microprocessor deals with data and makes access to the memory in units of a word or a byte, the memory areas M
1
and M
2
shown in
FIG. 1
have a word or byte structure. However, in image processing, a partial screen area to be processed is specified from the outside of the system without regard to the word boundary as shown by areas X
A
and X
B
in FIG.
1
. On this account, image processing for combining the partial areas X
A
and W
B
needs a modification unit MFY with the following three processing functions.
(1) Rearrangement of word data so that processing can take place on a word-wide basis between data for areas X
A
and X
B
with different starting bit positions na and nb.
(2) Separation of data section from word-wide data e.g., na bits, in each of addresses A
0
, A
3
, . . . ,A
n-2
so that it is retained unchanged in the processing.
(3) Data processing in any specific number of bits (bit width) so that monochrome display is implemented using one bit per pixel while color display uses a plurality of bits per pixel (generally four bits per pixel).
The operation of the modification unit having these functions will be described in connection with FIG.
2
. Throughout the following description, it is assumed that the image data memory is addressed in units of a word.
FIG. 2
shows a 2-word register SRC(A) and SRC(B) for storing data read out of the processing area X
B
, a 2-word register DST(A) and DST(B) for storing data read out of the processing area X
A
, and a 2-word register MRG(A) and MRG(B) for storing the result of processing for the contents of the registers SRC(A, B) and DST(A, B). The modification unit MFY performs rotation of the register SRC(A, B), i.e., shift of SRC content with bit
0
of SRC(A) linked with bit F of SRC(B), depending on the values of SN (i.e., nb) and DN (i.e., na) representing the starting bit positions of the processing areas X
A
and X
B
, as follows.
(a) For SN>DN: Rotates the SRC content left by a number of bits of SN-DN.
(b) For SN<DN: Rotate the SRC content right by a number of bits of DN-SN.
(c) For SN=DN: No operation.
In this way, bit addresses nb(SN) and na(DN) are used to align the operation starting bit position.
Consequently, the starting bit position of the SRC content is adjusted to that of the DST content. The bit width of processing, WN, is set in advance, and the remaining portion of data is left unchanged. Although in
FIG. 2
the result register MRG(A, B) is provided independently of DST(A, B), they may be arranged in common. After the subsequent processing, the original bit position of the SRC content is restored automatically.
Next, the 4-bit image processing for the areas X
A
and X
B
by the modification unit MFY will be described in connection with
FIGS. 3
,
4
,
5
and
6
. The process shown in
FIG. 3
includes step S
1
of setting the starting address A
0
for the processing area X
A
, step S2 of setting DN to the starting bit position (address) na, step S3 of setting the starting address B
0
for the processing area X
B
step S
4
of setting SN to the starting bit position (address) nb, step S
5
of the process implemented by the modification unit MFY mentioned above, steps S
6
-S
9
for the area XB for obtaining the next bit address (S
6
), setting the next SN (S
7
), incrementing the address in word units (S
8
) and reading next word data (S
9
), and steps S
10
-S
4
for the area X
B
for obtaining the next bit address (S
10
), setting the next DN (S
11
), writing the result of process in the register MRG (A) (S
12
), incrementing the address in word units (S
13
) and reading the next word data (S
14
). The process further includes decision steps SB
1
and SB
2
, which implement the following operations.
(I) Decision Step SB
1
This step tests as to whether the next SN address of SRC resulting from the steps S
6
and S
7
as in the following expression (
1
) reaches beyond the word boundary as in the following expression (
2
), and controls the sequence to fetch the next word data when the condition (
2
) is met.
SN=SN+WN
(1)
SN≧
(10)
HEX
(2)
(II) Decision Step SB
2
This step tests as to whether the next DN address of DST resulting from the steps S
10
and S
11
reaches beyond the word boundary as in the following expression (
3
), and controls the sequence to write data in the register MRG(A) to the area X
A
when the condition (
3
) is met, which indicates the end of operation at the current word boundary.
DN≧
(10)
HEX
(3)
The above operations for one raster (R
0
) will be described in more detail in connection with
FIGS. 4
,
5
, and
6
.
FIG. 4
is the case of condition,
DN
+
WN
=
(
A
)
HEX
+
(
4
)
HEX
<
(
10
)
HEX
Then, reading of the next word data and writing of process result do not take place.
FIG. 5
is the case of condition,
DN
+
WN
=
(
E
)
HEX
+
(
4
)
HEX
>
(
10
)
HEX
Then, reading of the next word data and writing of process result take place.
FIG. 6
is the case of condition,
SN
+
WN
=
(
D
)
HEX
+
(
4
)
HEX
>
(
10
)
HEX
and
DN
+
WN
=
(
2
)
HEX
+
(
4
)
HEX
<
(
10
)
HEX
Then, reading of the next SRC word data takes place, but writing of the process result does not take place.
Attempting to implement the image processing of the present invention using a conventional processing system involves the following drawbacks.
(1) The conventional microprocessor of word addressing type needs register rotation and word boundary check by software in implementing bit block operations, resulting in a complex system control.
(2) Fetching of data from the processing areas X
A
and X
B
needs different access timing depending on the current bit position with respect to the word boundary, resulting in a complex software control.
(3) The amount of data stored in the memory areas M
1
and M
2
will range as much as from 100 kilo-bytes to several mega-bytes, and the process shown in
FIG. 3
with the bit width WN being set as large as one byte (8 bits) will take a total number of steps of the order of 10
6
, and therefore the number of processing steps needs to be reduced drastically.
Furthermore, the conventional microprocessor merely allows bit operations such as arithmetic shift, logical shift, bit set, bit reset, etc. But as to other arithmetic and logic operations, etc., it is impossible to carry out the operations except only in a fixed bit length such as a byte or word.
On this account, in order to achieve “raster operation” on a bit-map display having a memory in correspondence at each point of on/off control to the display screen for implementing an image process between separate rectangular areas of arbitrary size on the screen, the above-mentioned bit
Aotsu Hiroaki
Kimura Koichi
Ogura Toshihiko
Urabe Kiichiro
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