Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-12-19
2003-03-11
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000
Reexamination Certificate
active
06532519
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to cache memories in general and, in particular, to an apparatus for controlling data allocation among cache memories within a multiprocessor data processing system. Still more particularly, the present invention relates to an apparatus for associating cache memories with processors within a symmetric multiprocessor data processing system.
2. Description of the Prior Art
In a symmetric multiprocessor (SMP) data-processing system, all of the processing units are generally identical; that is, they all have the same architecture and utilize a common set or subset of instructions and protocols to operate. Typically, each processing unit includes a processor core having at least one execution unit for carrying out program instructions. In addition, each processing unit may include at least one level of caches, commonly referred to as primary or L1 caches, which are typically implemented with high-speed memories. Similarly, a second level of caches, commonly referred to as secondary or L2 caches, may also be included in each processing unit for supporting the primary caches. Sometime, a third level of caches, commonly referred to as tertiary or L3 caches, may also be included in each processing unit for supporting the secondary caches. Each level of caches stores a subset of data and instructions contained in a system memory for low-latency accesses by various processor cores.
The present disclosure describes an apparatus for associating caches with various processing units within a symmetric multiprocessor data processing system.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a multiprocessor data processing system includes multiple processing units and multiple cache memories. Each of the cache memories includes a cache memory controller, and each cache memory controller includes a mode register. Each mode register has multiple processing unit fields, and each of the processing unit fields is associated with one of the processing units for indicating whether or not data from an associated processing unit should be cached by a cache memory associated to a corresponding cache memory controller.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5710881 (1998-01-01), Gupta et al.
patent: 6038642 (2000-03-01), Arimilli et al.
Arimilli Ravi Kumar
Fields, Jr. James Stephen
Ghai Sanjeev
Joyner Jody Bern
Bracewell & Patterson L.L.P.
Bragdon Reginald G.
Inoa Midys
International Business Machines - Corporation
Salys Casimer K.
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