Apparatus for and a method of detecting a malfunction of a FIFO

Static information storage and retrieval – Read/write circuit – Testing

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36518904, 36518907, 371 211, 371 212, G11C 700, G11C 2900

Patent

active

054043328

ABSTRACT:
A write address counter for designating a write address of a memory counts up a control counter with an address change. A read address counter for designating a read address of the memory counts down the control counter with the address change. Inputted to an error detecting circuit are a write address counter value, a read address counter value and a control count value. There is detected whether a relationship such as Write Address Count Value-Read Address Count Value=Control Count Value is established or not. If not established, this implies an error, and a reset circuit resets each counter.

REFERENCES:
patent: 5291449 (1994-03-01), Dehara
patent: 5305253 (1994-04-01), Ward
patent: 5309387 (1994-05-01), Mori
patent: 5311475 (1994-05-01), Huang

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