Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2000-02-09
2003-03-04
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S503000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06530030
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a an apparatus for and a method of clock tree synthesis allocation wiring in which clock buffers are wired to each other in a tree form to distribute a clock signal.
Description of the Prior Art
In the application specific integrated circuits (ASIC) of 0.5 micron generation, the wiring has a width of about 0.85 micron to about 0.96 micron, a film thickness of about 8000 angstrom (Å) to about 10000 Å, and a via size of about 0.8 micron. Additionally, these integrated circuits have a relatively low user system frequency, i.e., a maximum value of about 70 megaherz (MHz). In the clock tree allocation wiring with a fixed line width, even a capacity value which guarantees electro-migration at an available maximum frequency is set to as a maximum capacity value which can be added to a clock buffer, the capacity of the restriction value is large, i.e., about several picofarad (pF) when it is assumed that the wiring is conducted with a minimum wiring width. Consequently, there does not particularly arise any problem.
However, the system frequency has been considerably increased, for example, the integrated circuits of 0.35 micron rule generation have a maximum system frequency of about 150 MHz and those of 0.25 micron rule generation have a maximum system frequency of about 200 MHz. On the other hand, according to the 0.35 micron rule, the aluminum line width is about 0.65 micron to about 0.75 micron, the aluminum film thickness is about 6000 Å to about 7000 Å, and the via size is about 0.6 micron. In the integrated circuits of the 0.25 micron rule, the aluminum line width is about 0.4 micron to about 0.5 micron, the aluminum film thickness is about 4000 Å to about 5000 Å, and the via size is about 0.4 micron. In the clock tree allocation wiring with a fixed line width, to guarantee strength against electro-migration at a maximum allowable system frequency, if the wiring is assumed to be achieved with a minimum wiring width when the capacity value is fixed as in the prior art, the maximum capacity value which can be added to the clock buffer is reduced to a small value, namely, about 1 pF in the 0.35 micron generation and about 0.5 pF in the 0.25 micron generation. This is a very strict restriction for the users who desire to operate such integrated circuits at a low frequency. This increases the number of clock stages in the clock tree allocation wiring and resultantly leads to a problem of deterioration in performance, increase in consumption of operating power, and increase in production cost.
To solve the problem, when the pitch is doubled for the line width, the restriction of capacity is relieved. However, the wiring grid is doubled when compared with the circuit layout using the minimum line width. There consequently arises a new problem of great deterioration in efficiency of wiring. As another way of removing the problem, it may also be possible that a clock tree allocation wiring is provided to mitigate the limiting value of the capacity. Thereafter, a check is made to confirm whether or not the strength against electro-migration is guaranteed. At any position where the strength is not guaranteed, a new buffer is inserted to limit the capacity which is added to the buffer to thereby retain necessary reliability. However, due to insertion of buffers, there arises a new problem that the requirement of equal delay in all tree paths cannot be satisfied, namely, the delay value varies between a position with the additional buffer and a position without the buffer.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an apparatus for and a method of clock tree synthesis allocation wiring in which the wiring is appropriately achieved, the wiring cost is reduced, and the power consumption is minimized in operation.
To solve the problem above in accordance with a first aspect of the present invention, there is provided an apparatus for clock tree synthesis allocation wiring comprising a storage including a first file in which information of operating frequencies of clock lines is stored and a second file in which information of a maximum capacity allowed for a clock buffer for each operating frequency obtained according to restriction of electro-migration is stored, a maximum capacity determining a device connected to the storage, an input device for inputting therefrom to the maximum capacity determining device information of operating frequencies to be used, and a tool for clock tree synthesis allocation wiring connected to the maximum capacity determining device. The maximum capacity determining device determines a maximum available capacity allowed for each of the operating frequencies according to information of the operating frequency from the input device, information of the operating frequencies stored in the first file, and information of the maximum capacity stored in the second file. The wiring tool conducts wiring by assuming the maximum available capacity to be a limiting value of a maximum capacity which can be added to each clock buffer.
In accordance with a second aspect of the present invention, there is provided an apparatus for clock tree synthesis allocation wiring, comprising a storage including a first file in which information of operating frequencies of clock lines is stored and a second file in which information of a maximum capacity allowed for a clock buffer for each operating frequency obtained according to restriction of hot carrier degradation is stored, a maximum capacity determining device connected to the storage, an input device for inputting therefrom to the maximum capacity determining device information of operating frequencies to be used, and a tool for clock tree synthesis allocation wiring connected to the maximum capacity determining device. The maximum capacity determines device determining a maximum available capacity allowed for each of the operating frequencies according to information of the operating frequency from the input device, information of the operating frequencies stored in the first file, and information of the maximum capacity stored in the second file. The wiring tool conducts wiring by assuming the maximum available capacity to be a limiting value of a maximum capacity which can be added to each clock buffer.
In accordance with a third aspect of the present invention, there is provided an apparatus for clock tree synthesis allocation wiring, comprising a storage including a first file in which information of operating frequencies of clock lines is stored, a second file in which information of a maximum capacity allowed for a clock buffer for each operating frequency obtained according to restriction of electro-migration is stored, and a third file in which information of a maximum capacity allowed for a clock buffer for each operating frequency obtained according to restriction of hot carrier degradation is stored, a maximum capacity determining device connected to the storage, an input device for inputting therefrom to the maximum capacity determining device information of operating frequencies to be used, and a tool for clock tree synthesis allocation wiring connected to the maximum capacity determining device. The maximum capacity determines device determining a maximum available capacity allowed for each of the operating frequencies according to information of the operating frequency from the input device, information of the operating frequencies stored in the first file, and information of the maximum capacity stored in the second and third files. The wiring tool conducting wiring by assuming the maximum available capacity to be a limiting value of a maximum capacity which can be added to each clock buffer.
In accordance with a fourth aspect of the present invention, there is provided a method of clock tree synthesis allocation wiring for use with an apparatus for clock tree synthesis allocation wiring, the apparatus comprising a storage including a first file in which information of operati
Lee Thomas
Yanchus, III Paul B.
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