Apparatus for analyzing fault of semiconductor integrated...

Details Apparatus for analyzing fault of semiconductor integrated... Apparatus for analyzing fault of semiconductor integrated...

2007-10-16

2007-10-16

Bui, Bryan (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S108000, C324S765010

Reexamination Certificate

active

11484857

ABSTRACT:
A fault on a measuring point and information about a driving circuit of the fault are extracted. A signal value of a portion related to the fault on the measuring point and an input value of the driving circuit of the portion are obtained when a fault is not included. A fault candidate is extracted from detected faults based on a difference between a measured IDDQ value and a measured estimated IDDQ value when the fault is not included. An estimated calculation value to be a difference of an IDDQ value is calculated between a case when each of the faults is included and a case when the fault is not included. The estimated calculation value is compared with a difference between the measured value and the measured estimation value to decide whether or not the fault candidate is the fault corresponding to a defective portion.

REFERENCES:
patent: 6522159 (2003-02-01), Nishide
patent: 7096140 (2006-08-01), Nozuyama et al.
patent: 2004/0004493 (2004-01-01), Furukawa
patent: 09-292444 (1997-11-01), None
patent: 10-019986 (1998-01-01), None
“Decouple: Defect Current Detection in Deep Submicron IDDQ”, Proc. IEEE International Test Conference, pp. 199-206, 2000; Y.Okuda; Oct. 2000.

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