Apparatus for an energy efficient clustered micro-architecture

Details Apparatus for an energy efficient clustered micro-architecture Apparatus for an energy efficient clustered micro-architecture

2007-01-26

2010-02-02

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C712S200000

Reexamination Certificate

active

07657766

ABSTRACT:
In some embodiments, an apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the micro-architecture computes an energy delay2product for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delay2product is computed, the computed product is compared against an energy delay2product calculated for a prior architecture configuration to determine an effectiveness (energy efficiency) of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture. Other embodiments are described and claimed.

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