Apparatus for allowing data transfers with a memory having defec

Details Apparatus for allowing data transfers with a memory having defec Apparatus for allowing data transfers with a memory having defec

1997-03-04

1999-08-10

Le, Dieu-Minh T.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 7, 714 54, 714710, G06F 1100

Patent

active

059352582

ABSTRACT:
A memory fault correction system enables data to be written to and read from memory devices having a relatively large number of defective storage locations. For each address of the memory device, there are a plurality of storage locations corresponding in number to the number of bits of data to be stored, a plurality of substitute storage locations in which data is stored instead of being stored at defective memory locations, and a plurality of identifying locations in which data is stored identifying the defective memory locations at each address. In a write operation to an address, the identifying locations at the address are read to identify the defective memory locations at that address. The data that would otherwise be written to the defective memory locations is then instead written to the substitute memory locations. The remaining data is written to the corresponding locations at the address. In a read operation from the address, the data stored in the corresponding memory locations, the data stored in the substitute memory locations, and the data stored in the identifying memory locations are read. The data read from the substitute memory locations are then substituted for the data read from the defective memory locations as determined by the data read from the identifying locations at the address.

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