Apparatus for adjusting timing of memory signals

Details Apparatus for adjusting timing of memory signals Apparatus for adjusting timing of memory signals

2007-05-16

2008-08-26

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S400000, C713S401000, C713S503000, C711S100000

Reexamination Certificate

active

07418617

ABSTRACT:
An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit connected to the clock generator for receiving the reference signals, wherein the multiplexing unit selects a first reference signal according to a selecting signal; and an adjusting unit connected to the multiplexing unit for receiving a signal and delaying to output the signal according to the first reference signal selected by the multiplexing unit.

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