Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
2008-03-07
2010-11-02
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
C712S215000
Reexamination Certificate
active
07827388
ABSTRACT:
Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
REFERENCES:
patent: 4514803 (1985-04-01), Agnew et al.
patent: 4642756 (1987-02-01), Sherrod
patent: 5655115 (1997-08-01), Shen et al.
patent: 6073159 (2000-06-01), Emer et al.
patent: 6076157 (2000-06-01), Borkenhagen et al.
patent: 6105051 (2000-08-01), Borkenhagen et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6341347 (2002-01-01), Joy et al.
patent: 6477562 (2002-11-01), Nemirovsky et al.
patent: 6526421 (2003-02-01), Houldsworth
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 6542921 (2003-04-01), Sager
patent: 6567839 (2003-05-01), Borkenhagen et al.
patent: 6658447 (2003-12-01), Cota-Robles
patent: 6674536 (2004-01-01), Long et al.
patent: 6785890 (2004-08-01), Kalafatis et al.
patent: 6795845 (2004-09-01), Kalafatis et al.
patent: 6854118 (2005-02-01), Kalafatis et al.
patent: 6857004 (2005-02-01), Howard et al.
patent: 6865740 (2005-03-01), Kalafatis et al.
patent: 6910110 (2005-06-01), Kim et al.
patent: 6971104 (2005-11-01), Kalafatis et al.
patent: 6981261 (2005-12-01), Kalafatis et al.
patent: 7082519 (2006-07-01), Kelsey et al.
patent: 7120783 (2006-10-01), Fotland et al.
patent: 7149880 (2006-12-01), Kottapalli
patent: 2001/0056456 (2001-12-01), Cota-Robles
patent: 2002/0002667 (2002-01-01), Kelsey et al.
patent: 2002/0103990 (2002-08-01), Potash
patent: 2002/0129227 (2002-09-01), Arakawa
patent: 2003/0009648 (2003-01-01), Doing et al.
patent: 2003/0018686 (2003-01-01), Kalafatis et al.
patent: 2003/0023658 (2003-01-01), Kalafatis et al.
patent: 2003/0033345 (2003-02-01), Keefer et al.
patent: 2003/0154235 (2003-08-01), Sager
patent: 2004/0215945 (2004-10-01), Burky et al.
patent: 2005/0183072 (2005-08-01), Horning et al.
patent: 0 790 557 (1997-08-01), None
patent: 09-282184 (1997-10-01), None
patent: 10-124316 (1998-05-01), None
patent: 2000-020323 (2000-01-01), None
patent: 2001-306323 (2001-11-01), None
patent: WO 00/67113 (2000-11-01), None
patent: WO 02/067116 (2002-08-01), None
Luo, K. etal., Boosting SMT Performance by Speculation Control, 2001, IEEE , 8 pages.
Utiyama et al., “Design and Implementation of Multithreaded Processor for Real-Time Operation,” Technical Report of IEICE, vol. 99, No. 725 (Mar. 22, 2000), 8 pages.
Snavely et al “Symbiotic Jobscheduling for a Simultaneous Multithreading Processor,” SIGMETRICS Conf. Measurement and Modeling of C.S. (Jun. 2002), 11 pages.
Fiske et al., “Thread Priorization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors,” First International Symposium of High Performance Computer Architecture (Raleigh, NC, Jan. 1995), 14 pages.
Borkenhagen, et al., “A multithreaded PowerPC processor for commercial servers,” IBM J. Res. Develop, vol. 44, No. 6 (Nov. 2000), 14 pages.
Chang et al., “The Effects of Explicitly Parallel Mechanisms on the Multi-ALU Processor Cluster Pipeline,” IEEE (1998), 8 pages.
Darmon et al., “A New Pseudo-Random Interleaving For Antijamming Applications,” IEEE (1989), 5 pages.
Laudon et al., “Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations,” ACM (1994), 11 pages.
Lau, “Performance Analysis of Variable Rate: Symbol-by-Symbol Adaptive Bit Interleaved Coded Modulation for Rayleigh Fading Channels,” IEEE (2002), 14 pages.
Snavely et al., “Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor,” DRAFT Citeseer (Feb. 12, 2002), 24 pages.
Kalla Ronald Nick
Pham Minh Michelle Quy
Sinharoy Balaram
Ward, III John Wesley
Baca Matthew W.
Coleman Eric
Harris Andrew M.
International Business Machines - Corporation
Mitch Harris Atty at Law, LLC
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