Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-06-26
2001-10-23
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S137000, C712S205000, C712S207000
Reexamination Certificate
active
06308242
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a microprocessor; and, more particularly, to an improved prefetch control unit which is capable of effectively providing an improved prefetch operation based on various flush conditions.
DESCRIPTION OF THE PRIOR ART
A high performance microprocessor, such as a superscalar processor, is generally provided with a cache and a prefetch buffer or a prefetch queue in order to fetch instructions stored in an external main memory in a more effective manner. In this case, the performance of the processor can be improved by employing the cache and the prefetch buffer, while, since the complexity of the microprocessor is increased thereby, it is further difficult to control the complex elements such as the cache and the prefetch queue of the microprocessor. Referring to
FIG. 1
, there is shown a simplified block diagram of memory hierarchy which includes a main memory, a cache and a prefetch queue. The operational speed is gradually increased from the main memory to the prefetch queue, while the storage size is gradually increased from the prefetch queue to the main memory. The internal cache has an intermediate storage size and operational speed in comparison with the main memory and the prefetch queue. Although, in order to improve the performance of the microprocessor, the increased prefetch buffers can be employed therein, it is not a cost-effective manner because the cost of the prefetch buffer is relatively high. Therefore, in order to implement an optimum performance of the microprocessor in comparison with the cost thereof, it is needed to adjust a constructional ratio of three memory elements, i.e., the main memory, the internal cache and the prefetch queue.
An instruction fetch operation of the microprocessor is generally meant that, in order to execute the program, the instructions stored in a memory are sequentially read out from the memory. That is, since the instructions are stored in the memory in a series manner according to the execution sequence, the instructions can be sequentially fetched therefrom by continuously increasing the memory address therefor. On the other hand, an instruction prefetch operation thereof means that data, e.g., a series of instructions, contained in a program sequence to be executed are previously read out from the main memory and stored in the prefetch buffer having a higher operational speed capability.
However, during the sequential execution of the instructions, various flush conditions, in which the sequential execution is not required, are of frequent occurrence. The various flush conditions include a branch condition for executing a branch instruction, a segment limit violation or page fault condition, an external interrupt condition, a snoop hit condition and the like. In these case, the process is escaped from the current program sequence and goes to a newly designated program to be executed by using a newly provided address representing thereof. When there is no prefetch operation, it is merely required to change the program sequence. However, when the prefetch operation is used in the execution of the program sequence, i.e., the prefetch buffer is provided in the microprocessor, at some times, it is required that processing the flush condition should not be concurrent with the occurrence thereof. Therefore, it is needed that a decision circuit for dealing with the above problem is provided to the microprocessor having a prefetch buffer. When the program sequence changes, upon the decision from the decision circuit, invalid instructions prefetched and stored in the prefetch buffer is needed to be flushed and newly selected contents or instruction should be then prefetched and stored in the prefetch buffer.
Furthermore, it is desirable that a pipelined fetch and decode stage of the microprocessor is provided with means for determining whether the content stored in the prefetch buffer is valid.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide an apparatus, for use in a microprocessor having a prefetch queue which is capable of effectively providing an adaptive control of a prefetch queue based on various flush conditions.
In accordance with one aspect of the present invention, there is provided a microprocessor having an external memory for storing data, comprising: an internal cache for storing program data to be executed and for generating a first flush signal; a prefetch queue for storing a series of instructions contained in the program; a decode block for decoding the instructions and for generating a second flush signal; a buffer; and a control block, in response to the first flush signal, for storing an address and a state of instructions to be flushed into the buffer and, in response to the first flush signal and a third flush signal from an external device, for generating a queue flush signal to thereby flush the prefetch queue.
REFERENCES:
patent: 5317720 (1994-05-01), Stamm et al.
patent: 5515521 (1996-05-01), Whitted, III et al.
patent: 5606675 (1997-02-01), Sakamura et al.
patent: 5724549 (1998-03-01), Selgas et al.
patent: 6021485 (2000-02-01), Feiste et al.
Anderson Matthew D.
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Kim Matthew
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