Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
1998-06-30
2001-06-26
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S172000, C711S201000, C712S208000, C712S213000
Reexamination Certificate
active
06253276
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the design of a memory access structure in a computer system. More particularly, the present invention relates to a memory access structure, which provides fast decoding of memory type information for memory references that fall within a previously accessed module of memory.
2. Related Art
As processors clock speeds continue to increase, memory systems are under increasing pressure to provide data at faster rates to keep pace with the faster processors. This has recently led to the development of new memory chip designs, including page mode and extended data out (EDO) architectures, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory in a continuous stream using the processor clock. Such memory chips, with clocked interfaces are known as synchronous random access memories.
These new, faster memory chip designs are placing increasing pressure on associated memory controller circuitry to keep pace with the faster memory chips. In particular, memory controllers often include a decode block that must be accessed in a fraction of a memory cycle to retrieve characteristics of a memory module that is presently being accessed. These characteristics may include attributes such as memory speed, memory type and memory size, and are used by the memory controller to generate control signals for the requested memory access. With the faster memory cycle times, it is becoming increasingly harder to access the decode block in the required fraction of a memory cycle. Furthermore, as the number of varieties, sizes and access times supported by a memory controller increases, the amount of time required to decode the memory characteristics also increases.
What is needed is a system that generates characteristics of a memory module being accessed without a significant decoding delay.
SUMMARY
One embodiment of the present invention provides an apparatus for accessing a computer memory that bypasses decoding delays for memory type information within a memory controller. This apparatus includes a decoding circuit, for decoding a current address received from a processor to produce characteristics of a current memory module that is being accessed by the current address. These characteristics may include the size, type and speed of modules in the computer memory. The apparatus also includes a control signal generation circuit, for generating signals to control a memory access to the current address based upon the characteristics of the current memory module. The apparatus further includes a comparison module for determining whether the current address falls within a previously accessed memory module. The apparatus additionally includes a bypassing circuit. If the comparison module indicates that the current address falls within the previously accessed memory module, this bypassing circuit causes characteristics of a previously accessed memory module, obtained from a prior decoding of a previous address, to be used to generate the control signals for controlling the memory access. In a variation on this embodiment, if the comparison module indicates that the current address falls outside the previously accessed memory module, the bypassing circuit is causes characteristics of a memory module accessed by the current address to be used to generate the control signals.
In another variation, the comparison module is configured to identify a current memory module that being accessed by the current address, and to store information that can be used to determine upper and lower address boundaries for the current memory module.
Another variation includes a configuration mechanism that determines, upon system startup, characteristics of modules in the computer memory, and that uses these characteristics to configure the memory controller to generate accesses to the modules.
In another variation, the control signal generation circuit produces a module select signal.
In yet another variation, the control signal generation circuit produces control signals to selectively align upper and lower portions of the current address for input into a current memory module.
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patent: 5848258 (1998-12-01), Fenwick et al.
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Anderson Matthew D.
Kim Matthew
Micro)n Technology, Inc.
Park Vaughan & Fleming LLP
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