Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-04-22
2001-02-06
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S205000, C365S189090
Reexamination Certificate
active
06185142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sense amplifier, and more particularly, to a technique which is effective in decreasing the consumption of current and a surface area of a chip, and increasing an operation speed.
2. Description of the Related Art
FIG. 5
is a circuit diagram showing a part of a Dynamic Random-Access Memory (DRAM)
300
including the conventional open bit line system.
The DRAM
300
includes a memory cell MC, a dummy cell MD, a bit line BL for reading data stored in the memory cell MC, a bit line /BL for reading data stored in the dummy cell MD, a word line WL for selecting the memory cell MC, a dummy word line WD for selecting the dummy cell MD and a sense amplifier SA. The sense amplifier SA is operated by control signals &phgr;
1
and /&phgr;
1
.
FIG. 6
shows a signal wave shape in an operation of reading cell data in the nonvolatile memory
300
. First, during a precharge period (t
0
-t
1
), the bit lines BL and /BL are precharged and equalized by a precharge/equalization circuit (not shown) while the word line WL and the dummy word line WD are not activated.
For example, when the memory cell MC shown in
FIG. 6
is selected, the word line WL and the dummy word line WD corresponding thereto are activated at time t
1
, thereby generating a very small potential difference between the bit lines BL and /BL in response to the state of the stored charge in the memory cell MC.
Next, a sense amplifier SA is activated by the control signal &phgr;
1
at time t
2
, and a potential difference between a potential Vbit of the bit line BL and a potential /Vbit of the bit line /BL is sensed and latched.
Furthermore, one of the potentials Vbit and /Vbit is amplified so as to be a power supply potential Vdd, and the other of the potentials Vbit and /Vbit is amplified so as to be a ground potential GND. Thus, data is read out of and/or rewritten in the selected memory cell.
Japanese Laid-Open Publication No. 61-184794 discloses application of the above described configuration to a nonvolatile memory such as an EPROM (Erasable Programmable Read Only Memory), a Mask ROM (Mask programmable Read Only Memory) or the like. Such an application is possible because the consumption of current can be more easily decreased in a latch-type sense amplifier than a current mirror type differential amplifier.
In a memory cell of the conventional DRAM
300
shown in
FIG. 5
, a through current does not exist after the potential of the bit line BL is fixed. On the other hand, in a nonvolatile memory such as the EPROM, data is stored by the presence and absence of a current flowing in the memory cell transistor. Therefore, after the potential of the bit line BL is fixed, a conducting current of the memory cell continues to flow.
In the above described nonvolatile memory, a high potential cannot be applied to the bit line for a long period because of degradation of a voltage resistance of the memory cell caused by micronization, release of electric charges from a floating gate or the like.
In order to solve the above problems, transfer gates QA
1
and QA
2
are provided between the bit line BL and an input terminals of the sense amplifier SA, as shown in
FIG. 7
, so as to electrically separate the bit line BL and the sense amplifier SA after a sense/latch operation is completed. The sense amplifier SA is operated by control signals &phgr;
1
and /&phgr;
1
. The transfer gates QA
1
and QA
2
are operated by a control signal /&phgr;
2
.
Generally, in the nonvolatile memory, an open bit line system is not adopted. Data is read by comparing a potential Vbit of a bit line BL with a reference potential Vbit, which is commonly shared by the bit lines, in a sense amplifier SA.
FIG. 8
shows a conventional nonvolatile memory
400
.
The nonvolatile memory
400
includes a plurality of sense amplifiers SAA corresponding to a plurality of read data D
1
, D
2
and D
3
, and a reference potential generation circuit REF which is commonly used by the plurality of sense amplifiers SAA. The bit line RL is connected to an input terminal of the sense amplifier SAA. The common reference line RL is connected to the other input terminal of the sense amplifier SAA.
In the nonvolatile memory
400
shown in
FIG. 8
, the reference potential generation circuit REF sets a threshold value of the memory cell MD at the middle of on and off to generate an intermediate potential of the potential Vbit of the bit line BL, which acts as a reference potential Vref.
FIG. 9
shows a signal wave shape in an operation of reading cell data in the nonvolatile memory
400
.
During a precharge period (t
0
-t
1
), the bit line BL and the reference line RL are precharged and equalized by a precharge/equalization circuit (not shown). Next, for example, when the memory cell MC is selected, the word line WL and the reference potential generation circuit REF are activated at time t
1
. Thereby, a very small potential difference is generated between the bit line BL and the reference line RL in response to the state of the above memory cell MC (on or off). At time t
2
, the sense amplifier SAA is activated by a control signal &phgr;
1
, and a potential difference between the potential Vbit of the bit line BL and the reference potential Vref of the reference line RL is sensed and latched. After the latched data is fixed, at time t
3
, transfer gates QA
1
and QA
2
are turned off so as to disconnect the sense amplifier SAA and the bit line BL, and the sense amplifier SAA and the reference line RL, respectively.
Referring to the sense amplifier SAA in
FIG. 7
, since a load capacitance C
2
between an input of the sense amplifier SA and the transfer gate QA
1
and QA
2
is smaller than a bit line capacitance C
1
, in order to fix a latch stably, the disconnection of the transfer gate (t
3
) needs to be performed after the sense/latch operation is completed.
Japanese Laid-Open Publication No. 10-11975 discloses a configuration of a latch-type sense amplifier used for a SRAM (Static RAM), which is arranged for achieving a high speed operation and decreasing consumption of electric power.
FIG. 10
is a circuit diagram of a sense amplifier
500
which is designed for decreasing a consumption of electric power.
The sense amplifier
500
shown in
FIG. 10
includes a pair of N-type transistors QE
1
and QE
2
wherein drain electrodes thereof are connected to gate electrodes of each other so that each drain electrode acts as a sense output terminal, input transistors QE
3
to QE
6
which connect the potentials Vbit and /Vbit of the bit lines BL and /BL only to the gate electrodes, and P-type control transistors QE
7
and QE
8
which supply a load current to the sense output terminals through the input transistors QE
3
to QE
6
during an activation period.
In the above described open bit system, the bit lines are provided such that the sense amplifier is placed between the bit lines corresponding to the memory cells MC and the bit lines corresponding to the dummy memory cells MD, respectively. Therefore, it is necessary to provide dummy memories corresponding to respective bit lines. As a result, the surface area of a chip increases.
In the conventional nonvolatile memory, by rewriting data of the sense/latch operation during a period for reading data (t
2
-t
3
), a potential Vref of the reference line RL varies at the same time that a potential Vbit of the bit line BL varies. The potential Vref varies according to the potential Vbit of the bit line BL.
As shown in
FIG. 9
, the reference potential Vref moves in a direction opposite from a direction in which the potential Vbit of the bit line BL moves. When the memory cell is on, the potential Vbit of the bit line BL changes to a line Vbit (
0
) shown in
FIG. 9
, and the reference potential Vref changes to a line Vref (
0
) shown in FIG.
9
. When the memory cell is off, the potential Vbit of the bit line BL changes to a line Vbit (
1
) shown in
FIG. 9
, and the reference potential Vref changes to a line Vref (
1
) shown in FIG
9
. Therefore, a
Le Vu A.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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